drivers/clk/clk-stm32f4.c

29 #define STM32F4_RCC_CFGR		0x08  macro
420 	if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))  in clk_apb_mul_recalc_rate()
432 	if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))  in clk_apb_mul_round_rate()
1182 		STM32F4_RCC_CFGR, 23, 1,
1209 		STM32F4_RCC_CFGR, 23, 1,
1254 		STM32F4_RCC_CFGR, 23, 1,
1400 		STM32F4_RCC_CFGR, 23, 1,
1784 	    base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock);  in stm32f4_rcc_init()
1787 				   CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,  in stm32f4_rcc_init()
1791 				   CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,  in stm32f4_rcc_init()
1797 				   CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,  in stm32f4_rcc_init()
1848 			0, base + STM32F4_RCC_CFGR, 16, 5, 0,  in stm32f4_rcc_init()