Lines Matching +full:clk +full:- +full:output +full:- +full:sel
1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
58 /* The output stages can be connected to any synth (full mux) */
72 struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS]; member
73 struct clk *input_clk[SI5341_NUM_INPUTS];
121 /* Input dividers (48-bit) */
130 /* Output configuration */
131 #define SI5341_OUT_CONFIG(output) \ argument
132 ((output)->data->reg_output_offset[(output)->index])
133 #define SI5341_OUT_FORMAT(output) (SI5341_OUT_CONFIG(output) + 1) argument
134 #define SI5341_OUT_CM(output) (SI5341_OUT_CONFIG(output) + 2) argument
135 #define SI5341_OUT_MUX_SEL(output) (SI5341_OUT_CONFIG(output) + 3) argument
136 #define SI5341_OUT_R_REG(output) \ argument
137 ((output)->data->reg_rdiv_offset[(output)->index])
144 /* Synthesizer output enable, phase bypass, power mode */
167 /* Output configuration registers 0..9 are not quite logically organized */
212 * using only the XTAL input, without pre-divider.
214 * The "known" settings like synth and output configuration are done later.
357 /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */
409 err = si5341_decode_44_32(data->regmap, SI5341_PLL_M_NUM, in si5341_clk_recalc_rate()
418 * Though m_num is 64-bit, only the upper bits are actually used. While in si5341_clk_recalc_rate()
420 * the left. To avoid 96-bit division here, we just shift them back so in si5341_clk_recalc_rate()
433 data->freq_vco = res; in si5341_clk_recalc_rate()
446 err = regmap_read(data->regmap, SI5341_IN_SEL, &val); in si5341_clk_get_selected_input()
470 /* Enable register-based input selection */ in si5341_clk_reparent()
473 err = regmap_update_bits(data->regmap, in si5341_clk_reparent()
480 err = regmap_update_bits(data->regmap, in si5341_clk_reparent()
486 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN, in si5341_clk_reparent()
493 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG, in si5341_clk_reparent()
503 err = regmap_write(data->regmap, SI5341_IN_PDIV(index), 1); in si5341_clk_reparent()
507 err = regmap_write(data->regmap, SI5341_IN_PSET(index), 1); in si5341_clk_reparent()
512 err = regmap_write(data->regmap, SI5341_PX_UPD, BIT(index)); in si5341_clk_reparent()
517 err = regmap_update_bits(data->regmap, SI5341_IN_EN, 0x07, 0); in si5341_clk_reparent()
522 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN, in si5341_clk_reparent()
528 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG, in si5341_clk_reparent()
558 u8 index = synth->index; in si5341_synth_clk_is_on()
560 err = regmap_read(synth->data->regmap, in si5341_synth_clk_is_on()
568 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val); in si5341_synth_clk_is_on()
576 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val); in si5341_synth_clk_is_on()
586 u8 index = synth->index; /* In range 0..5 */ in si5341_synth_clk_unprepare()
589 /* Disable output */ in si5341_synth_clk_unprepare()
590 regmap_update_bits(synth->data->regmap, in si5341_synth_clk_unprepare()
593 regmap_update_bits(synth->data->regmap, in si5341_synth_clk_unprepare()
596 regmap_update_bits(synth->data->regmap, in si5341_synth_clk_unprepare()
604 u8 index = synth->index; in si5341_synth_clk_prepare()
608 err = regmap_update_bits(synth->data->regmap, in si5341_synth_clk_prepare()
614 err = regmap_update_bits(synth->data->regmap, in si5341_synth_clk_prepare()
619 /* Enable output */ in si5341_synth_clk_prepare()
620 return regmap_update_bits(synth->data->regmap, in si5341_synth_clk_prepare()
624 /* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */
634 err = si5341_decode_44_32(synth->data->regmap, in si5341_synth_clk_recalc_rate()
635 SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den); in si5341_synth_clk_recalc_rate()
644 * overflow in 64-bit math, we shift n_den 4 bits to the right in si5341_synth_clk_recalc_rate()
646 f = synth->data->freq_vco; in si5341_synth_clk_recalc_rate()
649 /* Now we need to to 64-bit division: f/n_num */ in si5341_synth_clk_recalc_rate()
663 f = synth->data->freq_vco; in si5341_synth_clk_round_rate()
668 f = synth->data->freq_vco; in si5341_synth_clk_round_rate()
680 u8 index = synth->index; in si5341_synth_program()
682 err = si5341_encode_44_32(synth->data->regmap, in si5341_synth_program()
685 err = regmap_update_bits(synth->data->regmap, in si5341_synth_program()
690 return regmap_write(synth->data->regmap, in si5341_synth_program()
705 n_num = synth->data->freq_vco; in si5341_synth_clk_set_rate()
721 dev_dbg(&synth->data->i2c_client->dev, in si5341_synth_clk_set_rate()
723 synth->index, n_num, n_den, in si5341_synth_clk_set_rate()
740 struct clk_si5341_output *output = to_clk_si5341_output(hw); in si5341_output_clk_is_on() local
744 err = regmap_read(output->data->regmap, in si5341_output_clk_is_on()
745 SI5341_OUT_CONFIG(output), &val); in si5341_output_clk_is_on()
749 /* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */ in si5341_output_clk_is_on()
753 /* Disables and then powers down the output */
756 struct clk_si5341_output *output = to_clk_si5341_output(hw); in si5341_output_clk_unprepare() local
758 regmap_update_bits(output->data->regmap, in si5341_output_clk_unprepare()
759 SI5341_OUT_CONFIG(output), in si5341_output_clk_unprepare()
761 regmap_update_bits(output->data->regmap, in si5341_output_clk_unprepare()
762 SI5341_OUT_CONFIG(output), in si5341_output_clk_unprepare()
766 /* Powers up and then enables the output */
769 struct clk_si5341_output *output = to_clk_si5341_output(hw); in si5341_output_clk_prepare() local
772 err = regmap_update_bits(output->data->regmap, in si5341_output_clk_prepare()
773 SI5341_OUT_CONFIG(output), in si5341_output_clk_prepare()
778 return regmap_update_bits(output->data->regmap, in si5341_output_clk_prepare()
779 SI5341_OUT_CONFIG(output), in si5341_output_clk_prepare()
786 struct clk_si5341_output *output = to_clk_si5341_output(hw); in si5341_output_clk_recalc_rate() local
792 err = regmap_read(output->data->regmap, in si5341_output_clk_recalc_rate()
793 SI5341_OUT_CONFIG(output), &val); in si5341_output_clk_recalc_rate()
801 err = regmap_bulk_read(output->data->regmap, in si5341_output_clk_recalc_rate()
802 SI5341_OUT_R_REG(output), r, 3); in si5341_output_clk_recalc_rate()
806 /* Calculate value as 24-bit integer*/ in si5341_output_clk_recalc_rate()
837 /* minimum r-divider is 2 */ in si5341_output_clk_round_rate()
856 struct clk_si5341_output *output = to_clk_si5341_output(hw); in si5341_output_clk_set_rate() local
862 return -EINVAL; in si5341_output_clk_set_rate()
870 r_div = BIT(24) - 1; in si5341_output_clk_set_rate()
872 --r_div; in si5341_output_clk_set_rate()
875 err = regmap_update_bits(output->data->regmap, in si5341_output_clk_set_rate()
876 SI5341_OUT_CONFIG(output), in si5341_output_clk_set_rate()
886 err = regmap_bulk_write(output->data->regmap, in si5341_output_clk_set_rate()
887 SI5341_OUT_R_REG(output), r, 3); in si5341_output_clk_set_rate()
892 static int si5341_output_reparent(struct clk_si5341_output *output, u8 index) in si5341_output_reparent() argument
894 return regmap_update_bits(output->data->regmap, in si5341_output_reparent()
895 SI5341_OUT_MUX_SEL(output), 0x07, index); in si5341_output_reparent()
900 struct clk_si5341_output *output = to_clk_si5341_output(hw); in si5341_output_set_parent() local
902 if (index >= output->data->num_synth) in si5341_output_set_parent()
903 return -EINVAL; in si5341_output_set_parent()
905 return si5341_output_reparent(output, index); in si5341_output_set_parent()
910 struct clk_si5341_output *output = to_clk_si5341_output(hw); in si5341_output_get_parent() local
913 regmap_read(output->data->regmap, SI5341_OUT_MUX_SEL(output), &val); in si5341_output_get_parent()
930 * The chip can be bought in a pre-programmed version, or one can program the
940 /* Read the PLL divider value, it must have a non-zero value */ in si5341_is_programmed_already()
941 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_DEN, in si5341_is_programmed_already()
953 unsigned int idx = clkspec->args[1]; in of_clk_si5341_get()
954 unsigned int group = clkspec->args[0]; in of_clk_si5341_get()
958 if (idx >= data->num_outputs) { in of_clk_si5341_get()
959 dev_err(&data->i2c_client->dev, in of_clk_si5341_get()
960 "invalid output index %u\n", idx); in of_clk_si5341_get()
961 return ERR_PTR(-EINVAL); in of_clk_si5341_get()
963 return &data->clk[idx].hw; in of_clk_si5341_get()
965 if (idx >= data->num_synth) { in of_clk_si5341_get()
966 dev_err(&data->i2c_client->dev, in of_clk_si5341_get()
968 return ERR_PTR(-EINVAL); in of_clk_si5341_get()
970 return &data->synth[idx].hw; in of_clk_si5341_get()
973 dev_err(&data->i2c_client->dev, in of_clk_si5341_get()
975 return ERR_PTR(-EINVAL); in of_clk_si5341_get()
977 return &data->hw; in of_clk_si5341_get()
979 dev_err(&data->i2c_client->dev, "invalid group %u\n", group); in of_clk_si5341_get()
980 return ERR_PTR(-EINVAL); in of_clk_si5341_get()
990 err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg, in si5341_probe_chip_id()
993 dev_err(&data->i2c_client->dev, "Failed to read chip ID\n"); in si5341_probe_chip_id()
999 dev_info(&data->i2c_client->dev, "Chip: %x Grade: %u Rev: %u\n", in si5341_probe_chip_id()
1004 data->num_outputs = SI5340_MAX_NUM_OUTPUTS; in si5341_probe_chip_id()
1005 data->num_synth = SI5340_NUM_SYNTH; in si5341_probe_chip_id()
1006 data->reg_output_offset = si5340_reg_output_offset; in si5341_probe_chip_id()
1007 data->reg_rdiv_offset = si5340_reg_rdiv_offset; in si5341_probe_chip_id()
1010 data->num_outputs = SI5341_MAX_NUM_OUTPUTS; in si5341_probe_chip_id()
1011 data->num_synth = SI5341_NUM_SYNTH; in si5341_probe_chip_id()
1012 data->reg_output_offset = si5341_reg_output_offset; in si5341_probe_chip_id()
1013 data->reg_rdiv_offset = si5341_reg_rdiv_offset; in si5341_probe_chip_id()
1016 data->num_outputs = SI5342_MAX_NUM_OUTPUTS; in si5341_probe_chip_id()
1017 data->num_synth = SI5342_NUM_SYNTH; in si5341_probe_chip_id()
1018 data->reg_output_offset = si5340_reg_output_offset; in si5341_probe_chip_id()
1019 data->reg_rdiv_offset = si5340_reg_rdiv_offset; in si5341_probe_chip_id()
1022 data->num_outputs = SI5344_MAX_NUM_OUTPUTS; in si5341_probe_chip_id()
1023 data->num_synth = SI5344_NUM_SYNTH; in si5341_probe_chip_id()
1024 data->reg_output_offset = si5340_reg_output_offset; in si5341_probe_chip_id()
1025 data->reg_rdiv_offset = si5340_reg_rdiv_offset; in si5341_probe_chip_id()
1028 data->num_outputs = SI5345_MAX_NUM_OUTPUTS; in si5341_probe_chip_id()
1029 data->num_synth = SI5345_NUM_SYNTH; in si5341_probe_chip_id()
1030 data->reg_output_offset = si5341_reg_output_offset; in si5341_probe_chip_id()
1031 data->reg_rdiv_offset = si5341_reg_rdiv_offset; in si5341_probe_chip_id()
1034 dev_err(&data->i2c_client->dev, "Model '%x' not supported\n", in si5341_probe_chip_id()
1036 return -EINVAL; in si5341_probe_chip_id()
1039 data->chip_id = model; in si5341_probe_chip_id()
1051 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_NUM, r, 10); in si5341_read_settings()
1055 err = regmap_bulk_read(data->regmap, in si5341_read_settings()
1060 err = regmap_bulk_read(data->regmap, in si5341_read_settings()
1065 for (i = 0; i < data->num_synth; ++i) { in si5341_read_settings()
1066 err = regmap_bulk_read(data->regmap, in si5341_read_settings()
1072 for (i = 0; i < data->num_outputs; ++i) { in si5341_read_settings()
1073 err = regmap_bulk_read(data->regmap, in si5341_read_settings()
1074 data->reg_output_offset[i], r, 4); in si5341_read_settings()
1078 err = regmap_bulk_read(data->regmap, in si5341_read_settings()
1079 data->reg_rdiv_offset[i], r, 3); in si5341_read_settings()
1094 res = regmap_write(data->regmap, in si5341_write_multiple()
1097 dev_err(&data->i2c_client->dev, in si5341_write_multiple()
1126 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision); in si5341_send_preamble()
1131 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xD8 : 0xC0); in si5341_send_preamble()
1136 if (data->chip_id > 0x5341) in si5341_send_preamble()
1151 /* Perform a soft reset and write post-amble */
1157 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision); in si5341_finalize_defaults()
1161 dev_dbg(&data->i2c_client->dev, "%s rev=%u\n", __func__, revision); in si5341_finalize_defaults()
1163 res = regmap_write(data->regmap, SI5341_SOFT_RST, 0x01); in si5341_finalize_defaults()
1167 /* The si5342..si5345 have an additional post-amble */ in si5341_finalize_defaults()
1168 if (data->chip_id > 0x5341) { in si5341_finalize_defaults()
1169 res = regmap_write(data->regmap, 0x540, 0x0); in si5341_finalize_defaults()
1175 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xDB : 0xC3); in si5341_finalize_defaults()
1178 res = regmap_write(data->regmap, 0x0B25, 0x02); in si5341_finalize_defaults()
1239 dev_err(&client->dev, "timeout waiting for DEVICE_READY\n"); in si5341_wait_device_ready()
1240 return -EIO; in si5341_wait_device_ready()
1257 struct device_node *np = client->dev.of_node; in si5341_dt_parse_dt()
1266 dev_err(&client->dev, "missing reg property of %s\n", in si5341_dt_parse_dt()
1267 child->name); in si5341_dt_parse_dt()
1272 dev_err(&client->dev, "invalid clkout %d\n", num); in si5341_dt_parse_dt()
1282 case 2: /* low-power differential */ in si5341_dt_parse_dt()
1291 dev_err(&client->dev, in si5341_dt_parse_dt()
1302 if (!of_property_read_u32(child, "silabs,common-mode", &val)) { in si5341_dt_parse_dt()
1304 dev_err(&client->dev, in si5341_dt_parse_dt()
1305 "invalid silabs,common-mode %u\n", in si5341_dt_parse_dt()
1315 dev_err(&client->dev, in si5341_dt_parse_dt()
1324 if (of_property_read_bool(child, "silabs,disable-high")) in si5341_dt_parse_dt()
1328 of_property_read_bool(child, "silabs,synth-master"); in si5341_dt_parse_dt()
1331 of_property_read_bool(child, "always-on"); in si5341_dt_parse_dt()
1338 return -EINVAL; in si5341_dt_parse_dt()
1342 * If not pre-configured, calculate and set the PLL configuration manually.
1343 * For low-jitter performance, the PLL should be set such that the synthesizers
1347 * may be sub-optimal.
1351 struct device_node *np = data->i2c_client->dev.of_node; in si5341_initialize_pll()
1354 int sel; in si5341_initialize_pll() local
1356 if (of_property_read_u32(np, "silabs,pll-m-num", &m_num)) { in si5341_initialize_pll()
1357 dev_err(&data->i2c_client->dev, in si5341_initialize_pll()
1358 "PLL configuration requires silabs,pll-m-num\n"); in si5341_initialize_pll()
1360 if (of_property_read_u32(np, "silabs,pll-m-den", &m_den)) { in si5341_initialize_pll()
1361 dev_err(&data->i2c_client->dev, in si5341_initialize_pll()
1362 "PLL configuration requires silabs,pll-m-den\n"); in si5341_initialize_pll()
1366 dev_err(&data->i2c_client->dev, in si5341_initialize_pll()
1368 sel = si5341_clk_get_selected_input(data); in si5341_initialize_pll()
1369 if (sel < 0) in si5341_initialize_pll()
1370 return sel; in si5341_initialize_pll()
1372 m_den = clk_get_rate(data->input_clk[sel]) / 10; in si5341_initialize_pll()
1376 return si5341_encode_44_32(data->regmap, in si5341_initialize_pll()
1391 if (!data->input_clk[res]) { in si5341_clk_select_active_input()
1392 dev_dbg(&data->i2c_client->dev, in si5341_clk_select_active_input()
1394 res = -ENODEV; in si5341_clk_select_active_input()
1396 if (data->input_clk[i]) { in si5341_clk_select_active_input()
1402 dev_err(&data->i2c_client->dev, in si5341_clk_select_active_input()
1413 err = clk_prepare_enable(data->input_clk[res]); in si5341_clk_select_active_input()
1425 struct clk *input; in si5341_probe()
1434 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); in si5341_probe()
1436 return -ENOMEM; in si5341_probe()
1438 data->i2c_client = client; in si5341_probe()
1446 input = devm_clk_get(&client->dev, si5341_input_clock_names[i]); in si5341_probe()
1448 if (PTR_ERR(input) == -EPROBE_DEFER) in si5341_probe()
1449 return -EPROBE_DEFER; in si5341_probe()
1450 data->input_clk_name[i] = si5341_input_clock_names[i]; in si5341_probe()
1452 data->input_clk[i] = input; in si5341_probe()
1453 data->input_clk_name[i] = __clk_get_name(input); in si5341_probe()
1461 if (of_property_read_string(client->dev.of_node, "clock-output-names", in si5341_probe()
1463 init.name = client->dev.of_node->name; in si5341_probe()
1466 data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config); in si5341_probe()
1467 if (IS_ERR(data->regmap)) in si5341_probe()
1468 return PTR_ERR(data->regmap); in si5341_probe()
1476 if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) { in si5341_probe()
1501 regcache_cache_only(data->regmap, true); in si5341_probe()
1523 init.parent_names = data->input_clk_name; in si5341_probe()
1527 data->hw.init = &init; in si5341_probe()
1529 err = devm_clk_hw_register(&client->dev, &data->hw); in si5341_probe()
1531 dev_err(&client->dev, "clock registration failed\n"); in si5341_probe()
1538 for (i = 0; i < data->num_synth; ++i) { in si5341_probe()
1539 synth_clock_names[i] = devm_kasprintf(&client->dev, GFP_KERNEL, in si5341_probe()
1540 "%s.N%u", client->dev.of_node->name, i); in si5341_probe()
1542 data->synth[i].index = i; in si5341_probe()
1543 data->synth[i].data = data; in si5341_probe()
1544 data->synth[i].hw.init = &init; in si5341_probe()
1545 err = devm_clk_hw_register(&client->dev, &data->synth[i].hw); in si5341_probe()
1547 dev_err(&client->dev, in si5341_probe()
1552 init.num_parents = data->num_synth; in si5341_probe()
1555 for (i = 0; i < data->num_outputs; ++i) { in si5341_probe()
1557 client->dev.of_node->name, i); in si5341_probe()
1559 data->clk[i].index = i; in si5341_probe()
1560 data->clk[i].data = data; in si5341_probe()
1561 data->clk[i].hw.init = &init; in si5341_probe()
1563 regmap_write(data->regmap, in si5341_probe()
1564 SI5341_OUT_FORMAT(&data->clk[i]), in si5341_probe()
1566 regmap_write(data->regmap, in si5341_probe()
1567 SI5341_OUT_CM(&data->clk[i]), in si5341_probe()
1570 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw); in si5341_probe()
1573 dev_err(&client->dev, in si5341_probe()
1574 "output %u registration failed\n", i); in si5341_probe()
1578 clk_prepare(data->clk[i].hw.clk); in si5341_probe()
1581 err = devm_of_clk_add_hw_provider(&client->dev, of_clk_si5341_get, in si5341_probe()
1584 dev_err(&client->dev, "unable to add clk provider\n"); in si5341_probe()
1590 regcache_cache_only(data->regmap, false); in si5341_probe()
1591 err = regcache_sync(data->regmap); in si5341_probe()
1601 err = regmap_read_poll_timeout(data->regmap, SI5341_STATUS, status, in si5341_probe()
1605 dev_err(&client->dev, "Error waiting for input clock or PLL lock\n"); in si5341_probe()
1610 err = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0); in si5341_probe()
1612 dev_err(&client->dev, "unable to clear sticky status\n"); in si5341_probe()
1616 /* Free the names, clk framework makes copies */ in si5341_probe()
1617 for (i = 0; i < data->num_synth; ++i) in si5341_probe()
1618 devm_kfree(&client->dev, (void *)synth_clock_names[i]); in si5341_probe()