Lines Matching refs:cg
79 void (*init_periph)(struct clockgen *cg);
100 static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg) in cg_out() argument
102 if (cg->info.flags & CG_LITTLE_ENDIAN) in cg_out()
108 static u32 cg_in(struct clockgen *cg, u32 __iomem *reg) in cg_in() argument
112 if (cg->info.flags & CG_LITTLE_ENDIAN) in cg_in()
467 static void __init p2041_init_periph(struct clockgen *cg) in p2041_init_periph() argument
471 reg = ioread32be(&cg->guts->rcwsr[7]); in p2041_init_periph()
474 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk; in p2041_init_periph()
476 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p2041_init_periph()
479 static void __init p4080_init_periph(struct clockgen *cg) in p4080_init_periph() argument
483 reg = ioread32be(&cg->guts->rcwsr[7]); in p4080_init_periph()
486 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; in p4080_init_periph()
488 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p4080_init_periph()
491 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; in p4080_init_periph()
493 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p4080_init_periph()
496 static void __init p5020_init_periph(struct clockgen *cg) in p5020_init_periph() argument
501 reg = ioread32be(&cg->guts->rcwsr[7]); in p5020_init_periph()
506 cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk; in p5020_init_periph()
508 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5020_init_periph()
511 static void __init p5040_init_periph(struct clockgen *cg) in p5040_init_periph() argument
516 reg = ioread32be(&cg->guts->rcwsr[7]); in p5040_init_periph()
521 cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk; in p5040_init_periph()
523 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5040_init_periph()
526 cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk; in p5040_init_periph()
528 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5040_init_periph()
531 static void __init t1023_init_periph(struct clockgen *cg) in t1023_init_periph() argument
533 cg->fman[0] = cg->hwaccel[1]; in t1023_init_periph()
536 static void __init t1040_init_periph(struct clockgen *cg) in t1040_init_periph() argument
538 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk; in t1040_init_periph()
541 static void __init t2080_init_periph(struct clockgen *cg) in t2080_init_periph() argument
543 cg->fman[0] = cg->hwaccel[0]; in t2080_init_periph()
546 static void __init t4240_init_periph(struct clockgen *cg) in t4240_init_periph() argument
548 cg->fman[0] = cg->hwaccel[3]; in t4240_init_periph()
549 cg->fman[1] = cg->hwaccel[4]; in t4240_init_periph()
812 struct clockgen *cg; member
833 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg); in mux_set_parent()
844 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in mux_get_parent()
868 static const struct clockgen_pll_div *get_pll_div(struct clockgen *cg, in get_pll_div() argument
880 return &cg->pll[pll].div[div]; in get_pll_div()
883 static struct clk * __init create_mux_common(struct clockgen *cg, in create_mux_common() argument
905 div = get_pll_div(cg, hwc, i); in create_mux_common()
931 hwc->cg = cg; in create_mux_common()
944 static struct clk * __init create_one_cmux(struct clockgen *cg, int idx) in create_one_cmux() argument
956 if (cg->info.flags & CG_VER3) in create_one_cmux()
957 hwc->reg = cg->regs + 0x70000 + 0x20 * idx; in create_one_cmux()
959 hwc->reg = cg->regs + 0x20 * idx; in create_one_cmux()
961 hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]]; in create_one_cmux()
970 clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in create_one_cmux()
971 div = get_pll_div(cg, hwc, clksel); in create_one_cmux()
981 plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk); in create_one_cmux()
983 if (cg->info.flags & CG_CMUX_GE_PLAT) in create_one_cmux()
988 return create_mux_common(cg, hwc, &cmux_ops, min_rate, max_rate, in create_one_cmux()
992 static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx) in create_one_hwaccel() argument
1000 hwc->reg = cg->regs + 0x20 * idx + 0x10; in create_one_hwaccel()
1001 hwc->info = cg->info.hwaccel[idx]; in create_one_hwaccel()
1003 return create_mux_common(cg, hwc, &hwaccel_ops, 0, ULONG_MAX, 0, in create_one_hwaccel()
1007 static void __init create_muxes(struct clockgen *cg) in create_muxes() argument
1011 for (i = 0; i < ARRAY_SIZE(cg->cmux); i++) { in create_muxes()
1012 if (cg->info.cmux_to_group[i] < 0) in create_muxes()
1014 if (cg->info.cmux_to_group[i] >= in create_muxes()
1015 ARRAY_SIZE(cg->info.cmux_groups)) { in create_muxes()
1020 cg->cmux[i] = create_one_cmux(cg, i); in create_muxes()
1023 for (i = 0; i < ARRAY_SIZE(cg->hwaccel); i++) { in create_muxes()
1024 if (!cg->info.hwaccel[i]) in create_muxes()
1027 cg->hwaccel[i] = create_one_hwaccel(cg, i); in create_muxes()
1185 static void __init create_one_pll(struct clockgen *cg, int idx) in create_one_pll() argument
1189 struct clockgen_pll *pll = &cg->pll[idx]; in create_one_pll()
1193 if (!(cg->info.pll_mask & (1 << idx))) in create_one_pll()
1196 if (cg->coreclk && idx != PLATFORM_PLL) { in create_one_pll()
1197 if (IS_ERR(cg->coreclk)) in create_one_pll()
1203 if (cg->info.flags & CG_VER3) { in create_one_pll()
1206 reg = cg->regs + 0x60080; in create_one_pll()
1209 reg = cg->regs + 0x80; in create_one_pll()
1212 reg = cg->regs + 0xa0; in create_one_pll()
1215 reg = cg->regs + 0x10080; in create_one_pll()
1218 reg = cg->regs + 0x100a0; in create_one_pll()
1226 reg = cg->regs + 0xc00; in create_one_pll()
1228 reg = cg->regs + 0x800 + 0x20 * (idx - 1); in create_one_pll()
1232 mult = cg_in(cg, reg); in create_one_pll()
1240 if ((cg->info.flags & CG_VER3) || in create_one_pll()
1241 ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL)) in create_one_pll()
1277 static void __init create_plls(struct clockgen *cg) in create_plls() argument
1281 for (i = 0; i < ARRAY_SIZE(cg->pll); i++) in create_plls()
1282 create_one_pll(cg, i); in create_plls()
1363 struct clockgen *cg = data; in clockgen_clk_get() local
1380 clk = cg->sysclk; in clockgen_clk_get()
1383 if (idx >= ARRAY_SIZE(cg->cmux)) in clockgen_clk_get()
1385 clk = cg->cmux[idx]; in clockgen_clk_get()
1388 if (idx >= ARRAY_SIZE(cg->hwaccel)) in clockgen_clk_get()
1390 clk = cg->hwaccel[idx]; in clockgen_clk_get()
1393 if (idx >= ARRAY_SIZE(cg->fman)) in clockgen_clk_get()
1395 clk = cg->fman[idx]; in clockgen_clk_get()
1398 pll = &cg->pll[PLATFORM_PLL]; in clockgen_clk_get()
1406 clk = cg->coreclk; in clockgen_clk_get()