Lines Matching refs:PLL_DIV4
25 #define PLL_DIV4 3 macro
211 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
215 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
219 { CLKSEL_VALID, CGA_PLL3, PLL_DIV4 },
227 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
231 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
239 { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
243 { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
251 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
261 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
274 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
287 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
300 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
335 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
360 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
373 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
409 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
422 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
435 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
446 [4] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
456 [4] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
503 div = PLL_DIV4; in p5020_init_periph()
518 div = PLL_DIV4; in p5040_init_periph()