23 #define PLL_DIV2	1  macro
123 		[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
132 		[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
139 		[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
148 		[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
155 		[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
157 		[5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 },
164 		[1] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV2 },
166 		[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
173 		[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
175 		[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
184 		[9] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
186 		[13] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV2 },
193 		[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
200 		[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
202 		[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
210 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
214 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
218 		{ CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
226 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
230 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
238 		{ CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
242 		{ CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
250 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
259 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
263 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
272 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
276 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
285 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
289 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
298 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
302 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
311 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
315 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
333 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
337 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
346 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
350 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
358 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
362 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
371 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
375 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
384 		[2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
392 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
399 		[6] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
407 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
411 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
420 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
424 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
431 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 },
433 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
437 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
444 		[2] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
448 		[6] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
454 		[2] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
458 		[6] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
474 		cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk;  in p2041_init_periph()
476 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p2041_init_periph()
486 		cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;  in p4080_init_periph()
488 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p4080_init_periph()
491 		cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;  in p4080_init_periph()
493 		cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p4080_init_periph()
499 	int div = PLL_DIV2;  in p5020_init_periph()
508 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p5020_init_periph()
514 	int div = PLL_DIV2;  in p5040_init_periph()
523 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p5040_init_periph()
528 		cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p5040_init_periph()