drivers/clk/clk-qoriq.c

22 #define PLL_DIV1	0  macro
122 		[0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
124 		[4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
130 		[0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
131 		[4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
138 		[0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
140 		[4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
146 		[0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
147 		[4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
154 		[0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
156 		[4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
163 		[0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
165 		[4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
172 		[0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
174 		[4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
176 		[8] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL3, PLL_DIV1 },
182 		[0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
183 		[8] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
185 		[12] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV1 },
192 		[0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
199 		[0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
201 		[4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
209 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
213 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
217 		{ CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
225 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
229 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
237 		{ CLKSEL_VALID, CGB_PLL1, PLL_DIV1 },
241 		{ CLKSEL_VALID, CGB_PLL2, PLL_DIV1 },
249 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
257 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
258 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
270 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
271 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
283 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
284 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
296 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
297 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
323 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
336 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
345 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
357 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
370 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
382 		[0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
391 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
406 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
410 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
419 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
423 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
432 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
447 		[5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
457 		[5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
538 	cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk;  in t1040_init_periph()
981 	plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);  in create_one_cmux()