drivers/clk/clk-qoriq.c

29 #define CGA_PLL2	2  macro
124 		[4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
131 		[4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
132 		[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
140 		[4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
147 		[4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
148 		[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
156 		[4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
157 		[5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 },
165 		[4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
166 		[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
174 		[4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
175 		[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
201 		[4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
202 		[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
213 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
214 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
215 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
229 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
230 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
231 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
263 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
264 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
271 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
272 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
273 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
274 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
289 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
290 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
297 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
298 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
299 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
300 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
315 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
316 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
323 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
325 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
337 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
338 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
345 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
346 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
347 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
362 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
363 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
370 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
371 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
372 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
373 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
411 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
412 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
419 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
420 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
421 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
422 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
437 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
438 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
474 		cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk;  in p2041_init_periph()
506 		cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk;  in p5020_init_periph()
1211 		case CGA_PLL2:  in create_one_pll()