Lines Matching refs:CLKSEL
17 #define CLKSEL(n) (((n) - 1) * 4 + M10V_CLKSEL1) macro
254 {"emmc", M10V_PLL11, CLKSEL(1), 28, 3, emmcclk_table, 0,
256 {"mclk400", M10V_PLL1DIV2, CLKSEL(10), 7, 3, mclk400_table, 0, -1},
257 {"mclk200", M10V_PLL1DIV2, CLKSEL(10), 3, 4, mclk200_table, 0, -1},
258 {"aclk400", M10V_PLL1DIV2, CLKSEL(10), 0, 3, aclk400_table, 0, -1},
259 {"aclk300", M10V_PLL2DIV2, CLKSEL(12), 0, 2, aclk300_table, 0, -1},
260 {"aclk", M10V_PLL1DIV2, CLKSEL(9), 20, 4, aclk_table, 0, M10V_ACLK_ID},
261 {"aclkexs", M10V_PLL1DIV2, CLKSEL(9), 16, 4, aclkexs_table, 0, -1},
262 {"hclk", M10V_PLL1DIV2, CLKSEL(9), 7, 5, hclk_table, 0, M10V_HCLK_ID},
263 {"hclkbmh", M10V_PLL1DIV2, CLKSEL(9), 12, 4, hclkbmh_table, 0, -1},
264 {"pclk", M10V_PLL1DIV2, CLKSEL(9), 0, 7, pclk_table, 0, M10V_PCLK_ID},
265 {"uhs1clk0", M10V_PLL7, CLKSEL(1), 3, 5, uhs1clk0_table, 0, -1},
266 {"uhs2clk", M10V_PLL6DIV3, CLKSEL(1), 18, 4, uhs2clk_table, 0, -1},
271 CLKSEL(8), 3, 7, spi_mux_table, 0, M10V_SPICLK_ID},
273 CLKSEL(1), 13, 31, uhs1clk2_mux_table, 0, M10V_UHS1CLK2_ID},
275 CLKSEL(1), 8, 31, uhs1clk1_mux_table, 0, -1},
277 CLKSEL(1), 22, 127, nfclk_mux_table, 0, M10V_NFCLK_ID},
509 if ((factors->offset == CLKSEL(9)) || (factors->offset == CLKSEL(10))) in m10v_reg_div_pre()
510 write_valid_reg = base + CLKSEL(11); in m10v_reg_div_pre()
656 base + CLKSEL(1), 0, 3, 0, rclk_table, in m10v_cc_init()