490 	u32 ctl_reg;  member
511 	u32 ctl_reg;  member
931 	return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0;  in bcm2835_clock_is_on()
1020 	while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) {  in bcm2835_clock_wait_busy()
1037 	cprman_write(cprman, data->ctl_reg,  in bcm2835_clock_off()
1038 		     cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE);  in bcm2835_clock_off()
1052 	cprman_write(cprman, data->ctl_reg,  in bcm2835_clock_on()
1053 		     cprman_read(cprman, data->ctl_reg) |  in bcm2835_clock_on()
1091 	ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;  in bcm2835_clock_set_rate()
1093 	cprman_write(cprman, data->ctl_reg, ctl);  in bcm2835_clock_set_rate()
1241 	cprman_write(cprman, data->ctl_reg, src);  in bcm2835_clock_set_parent()
1250 	u32 src = cprman_read(cprman, data->ctl_reg);  in bcm2835_clock_get_parent()
1273 	bcm2835_debugfs_regset(cprman, data->ctl_reg,  in bcm2835_clock_debug_init()
1451 		if (!(cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE))  in bcm2835_register_clock()
1477 				    cprman->regs + gate_data->ctl_reg,  in bcm2835_register_gate()
1916 		.ctl_reg = CM_OTPCTL,
1928 		.ctl_reg = CM_TIMERCTL,
1939 		.ctl_reg = CM_TSENSCTL,
1946 		.ctl_reg = CM_TECCTL,
1955 		.ctl_reg = CM_H264CTL,
1963 		.ctl_reg = CM_ISPCTL,
1976 		.ctl_reg = CM_SDCCTL,
1984 		.ctl_reg = CM_V3DCTL,
1998 		.ctl_reg = CM_VPUCTL,
2010 		.ctl_reg = CM_AVEOCTL,
2018 		.ctl_reg = CM_CAM0CTL,
2026 		.ctl_reg = CM_CAM1CTL,
2034 		.ctl_reg = CM_DFTCTL,
2041 		.ctl_reg = CM_DPICTL,
2051 		.ctl_reg = CM_EMMCCTL,
2061 		.ctl_reg = CM_EMMC2CTL,
2071 		.ctl_reg = CM_GP0CTL,
2080 		.ctl_reg = CM_GP1CTL,
2090 		.ctl_reg = CM_GP2CTL,
2100 		.ctl_reg = CM_HSMCTL,
2108 		.ctl_reg = CM_PCMCTL,
2118 		.ctl_reg = CM_PWMCTL,
2127 		.ctl_reg = CM_SLIMCTL,
2136 		.ctl_reg = CM_SMICTL,
2144 		.ctl_reg = CM_UARTCTL,
2154 		.ctl_reg = CM_VECCTL,
2169 		.ctl_reg = CM_DSI0ECTL,
2177 		.ctl_reg = CM_DSI1ECTL,
2185 		.ctl_reg = CM_DSI0PCTL,
2193 		.ctl_reg = CM_DSI1PCTL,
2211 		.ctl_reg = CM_PERIICTL),