Lines Matching refs:REGISTER_PLL_DIV

1496 #define REGISTER_PLL_DIV(s, ...) _REGISTER(&bcm2835_register_pll_divider, \  macro
1661 	[BCM2835_PLLA_CORE]	= REGISTER_PLL_DIV(
1671 	[BCM2835_PLLA_PER]	= REGISTER_PLL_DIV(
1681 	[BCM2835_PLLA_DSI0]	= REGISTER_PLL_DIV(
1690 	[BCM2835_PLLA_CCP2]	= REGISTER_PLL_DIV(
1718 	[BCM2835_PLLB_ARM]	= REGISTER_PLL_DIV(
1750 	[BCM2835_PLLC_CORE0]	= REGISTER_PLL_DIV(
1760 	[BCM2835_PLLC_CORE1]	= REGISTER_PLL_DIV(
1770 	[BCM2835_PLLC_CORE2]	= REGISTER_PLL_DIV(
1780 	[BCM2835_PLLC_PER]	= REGISTER_PLL_DIV(
1812 	[BCM2835_PLLD_CORE]	= REGISTER_PLL_DIV(
1827 	[BCM2835_PLLD_PER]	= REGISTER_PLL_DIV(
1837 	[BCM2835_PLLD_DSI0]	= REGISTER_PLL_DIV(
1846 	[BCM2835_PLLD_DSI1]	= REGISTER_PLL_DIV(
1877 	[BCM2835_PLLH_RCAL]	= REGISTER_PLL_DIV(
1887 	[BCM2835_PLLH_AUX]	= REGISTER_PLL_DIV(
1897 	[BCM2835_PLLH_PIX]	= REGISTER_PLL_DIV(