Lines Matching full:eth_clk
156 CCU_DIV_VAR_INFO(CCU_AXI_GMAC0_CLK, "axi_gmac0_clk", "eth_clk",
159 CCU_DIV_VAR_INFO(CCU_AXI_GMAC1_CLK, "axi_gmac1_clk", "eth_clk",
162 CCU_DIV_VAR_INFO(CCU_AXI_XGMAC_CLK, "axi_xgmac_clk", "eth_clk",
177 CCU_DIV_VAR_INFO(CCU_AXI_SRAM_CLK, "axi_sram_clk", "eth_clk",
213 "eth_clk", CCU_SYS_GMAC0_BASE, 5),
215 "eth_clk", 10),
217 "eth_clk", CCU_SYS_GMAC1_BASE, 5),
219 "eth_clk", 10),
221 "eth_clk", CCU_SYS_XGMAC_BASE, 1),
227 "eth_clk", CCU_SYS_USB_BASE, 10),
235 "eth_clk", CCU_SYS_UART_BASE, 17,
238 "eth_clk", 10),
240 "eth_clk", 10),
253 "eth_clk", CCU_SYS_WDT_BASE, 17,