Lines Matching full:divider
79 unsigned long divider) in ccu_div_var_update_clkdiv() argument
86 nd = ccu_div_lock_delay_ns(parent_rate, divider); in ccu_div_var_update_clkdiv()
136 pr_err("Divider '%s' lock timed out\n", clk_hw_get_name(hw)); in ccu_div_var_enable()
212 unsigned long divider; in ccu_div_var_recalc_rate() local
216 divider = ccu_div_get(div->mask, val); in ccu_div_var_recalc_rate()
218 return ccu_div_calc_freq(parent_rate, divider); in ccu_div_var_recalc_rate()
225 unsigned long divider; in ccu_div_var_calc_divider() local
227 divider = parent_rate / rate; in ccu_div_var_calc_divider()
228 return clamp_t(unsigned long, divider, CCU_DIV_CLKDIV_MIN, in ccu_div_var_calc_divider()
236 unsigned long divider; in ccu_div_var_round_rate() local
238 divider = ccu_div_var_calc_divider(rate, *parent_rate, div->mask); in ccu_div_var_round_rate()
240 return ccu_div_calc_freq(*parent_rate, divider); in ccu_div_var_round_rate()
244 * This method is used for the clock divider blocks, which support the
252 unsigned long flags, divider; in ccu_div_var_set_rate_slow() local
256 divider = ccu_div_var_calc_divider(rate, parent_rate, div->mask); in ccu_div_var_set_rate_slow()
257 if (divider == 1 && div->features & CCU_DIV_SKIP_ONE) { in ccu_div_var_set_rate_slow()
258 divider = 0; in ccu_div_var_set_rate_slow()
260 if (divider == 1 || divider == 2) in ccu_div_var_set_rate_slow()
261 divider = 0; in ccu_div_var_set_rate_slow()
262 else if (divider == 3) in ccu_div_var_set_rate_slow()
263 divider = 4; in ccu_div_var_set_rate_slow()
266 val = ccu_div_prep(div->mask, divider); in ccu_div_var_set_rate_slow()
270 ret = ccu_div_var_update_clkdiv(div, parent_rate, divider); in ccu_div_var_set_rate_slow()
273 pr_err("Divider '%s' lock timed out\n", clk_hw_get_name(hw)); in ccu_div_var_set_rate_slow()
279 * This method is used for the clock divider blocks, which don't support
286 unsigned long flags, divider; in ccu_div_var_set_rate_fast() local
289 divider = ccu_div_var_calc_divider(rate, parent_rate, div->mask); in ccu_div_var_set_rate_fast()
290 val = ccu_div_prep(div->mask, divider); in ccu_div_var_set_rate_fast()
293 * Also disable the clock divider block if it was enabled by default in ccu_div_var_set_rate_fast()
309 return ccu_div_calc_freq(parent_rate, div->divider); in ccu_div_fixed_recalc_rate()
317 return ccu_div_calc_freq(*parent_rate, div->divider); in ccu_div_fixed_round_rate()
368 * It can be dangerous to change the Divider settings behind clock framework
447 *val = div->divider; in ccu_div_dbgfs_fixed_clkdiv_get()
630 div->divider = div_init->divider; in ccu_div_hw_register()
635 div->divider = div_init->divider; in ccu_div_hw_register()