Lines Matching refs:CHB
240 #define CHB 0x40 /* channel B offset */ macro
343 write_reg16(info, CHB + IMR, info->imrb_value); in irq_disable()
353 write_reg16(info, CHB + IMR, info->imrb_value); in irq_enable()
1051 irq_disable(info, CHB, IRQ_CTS); in cts_change()
1086 irq_disable(info, CHB, IRQ_DCD); in dcd_change()
1186 isr = read_reg16(info, CHB + ISR); in mgslpc_isr()
1389 irq_enable(info, CHB, IRQ_DCD | IRQ_CTS); in mgslpc_program_hw()
2926 write_reg(info, CHB + MODE, val); in enable_auxclk()
2938 write_reg(info, CHB + CCR0, 0xc0); in enable_auxclk()
2951 write_reg(info, CHB + CCR1, 0x17); in enable_auxclk()
2966 write_reg(info, CHB + CCR2, 0x38); in enable_auxclk()
2968 write_reg(info, CHB + CCR2, 0x30); in enable_auxclk()
2981 write_reg(info, CHB + CCR4, 0x50); in enable_auxclk()
2987 mgslpc_set_rate(info, CHB, info->params.clock_speed); in enable_auxclk()
2989 mgslpc_set_rate(info, CHB, 921600); in enable_auxclk()
3022 irq_disable(info, CHB, 0xffff); in hdlc_mode()
3223 irq_enable(info, CHB, IRQ_CTS); in hdlc_mode()
3340 write_reg(info, CHB + CCR0, 0x80); in reset_device()
3342 write_reg(info, CHB + MODE, 0); in reset_device()
3346 irq_disable(info, CHB, 0xffff); in reset_device()
3392 irq_disable(info, CHB, 0xffff); in async_mode()
3542 irq_enable(info, CHB, IRQ_CTS); in async_mode()
3575 if (read_reg(info, CHB + VSTR) & BIT7) in get_signals()
3577 if (read_reg(info, CHB + STAR) & BIT1) in get_signals()