239 #define CHA     0x00   /* channel A offset */  macro
338 	if (channel == CHA) {  in irq_disable()
340 		write_reg16(info, CHA + IMR, info->imra_value);  in irq_disable()
348 	if (channel == CHA) {  in irq_enable()
350 		write_reg16(info, CHA + IMR, info->imra_value);  in irq_enable()
844 		issue_command(info, CHA, CMD_RXRESET);  in rx_ready_hdlc()
853 		fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);  in rx_ready_hdlc()
862 			data[0] = read_reg(info, CHA + RXFIFO);  in rx_ready_hdlc()
865 			*((unsigned short *) data) = read_reg16(info, CHA + RXFIFO);  in rx_ready_hdlc()
874 				issue_command(info, CHA, CMD_RXRESET);  in rx_ready_hdlc()
890 	issue_command(info, CHA, CMD_RXFIFO);  in rx_ready_hdlc()
903 		fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);  in rx_ready_async()
908 		if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5))  in rx_ready_async()
916 		data   = read_reg(info, CHA + RXFIFO);  in rx_ready_async()
917 		status = read_reg(info, CHA + RXFIFO);  in rx_ready_async()
946 	issue_command(info, CHA, CMD_RXFIFO);  in rx_ready_async()
1025 			write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get));  in tx_ready()
1027 			write_reg16(info, CHA + TXFIFO,  in tx_ready()
1038 		issue_command(info, CHA, CMD_TXFIFO);  in tx_ready()
1041 			issue_command(info, CHA, CMD_TXFIFO);  in tx_ready()
1043 			issue_command(info, CHA, CMD_TXFIFO + CMD_TXEOM);  in tx_ready()
1175 	while ((gis = read_reg(info, CHA + GIS))) {  in mgslpc_isr()
1194 			isr = read_reg16(info, CHA + ISR);  in mgslpc_isr()
1197 				irq_disable(info, CHA, IRQ_TIMER);  in mgslpc_isr()
1211 				issue_command(info, CHA, CMD_RXFIFO_READ);  in mgslpc_isr()
1236 			pis = read_reg(info, CHA + PIS);  in mgslpc_isr()
1992 		irq_enable(info, CHA, IRQ_EXITHUNT);  in wait_events()
2053 			irq_disable(info, CHA, IRQ_EXITHUNT);  in wait_events()
2184 		set_reg_bits(info, CHA+DAFO, BIT6);  in mgslpc_break()
2186 		clear_reg_bits(info, CHA+DAFO, BIT6);  in mgslpc_break()
2997 	val = read_reg(info, CHA + CCR1) | (BIT2 | BIT1 | BIT0);  in loopback_enable()
2998 	write_reg(info, CHA + CCR1, val);  in loopback_enable()
3001 	val = read_reg(info, CHA + CCR2) | (BIT4 | BIT5);  in loopback_enable()
3002 	write_reg(info, CHA + CCR2, val);  in loopback_enable()
3006 		mgslpc_set_rate(info, CHA, info->params.clock_speed);  in loopback_enable()
3008 		mgslpc_set_rate(info, CHA, 1843200);  in loopback_enable()
3011 	val = read_reg(info, CHA + MODE) | BIT0;  in loopback_enable()
3012 	write_reg(info, CHA + MODE, val);  in loopback_enable()
3021 	irq_disable(info, CHA, 0xffff);  in hdlc_mode()
3069 	write_reg(info, CHA + MODE, val);  in hdlc_mode()
3097 	write_reg(info, CHA + CCR0, val);  in hdlc_mode()
3111 	write_reg(info, CHA + CCR1, val);  in hdlc_mode()
3135 	write_reg(info, CHA + CCR2, val);  in hdlc_mode()
3166 	write_reg(info, CHA + CCR3, val);  in hdlc_mode()
3177 	write_reg(info, CHA + PRE, val);  in hdlc_mode()
3191 	write_reg(info, CHA + CCR4, val);  in hdlc_mode()
3193 		mgslpc_set_rate(info, CHA, info->params.clock_speed * 16);  in hdlc_mode()
3195 		mgslpc_set_rate(info, CHA, info->params.clock_speed);  in hdlc_mode()
3202 	write_reg(info, CHA + RLCR, 0);  in hdlc_mode()
3217 	write_reg(info, CHA + XBCH, val);  in hdlc_mode()
3225 		set_reg_bits(info, CHA + PVR, BIT3);  in hdlc_mode()
3227 		clear_reg_bits(info, CHA + PVR, BIT3);  in hdlc_mode()
3229 	irq_enable(info, CHA,  in hdlc_mode()
3232 	issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);  in hdlc_mode()
3233 	wait_command_complete(info, CHA);  in hdlc_mode()
3234 	read_reg16(info, CHA + ISR);	/* clear pending IRQs */  in hdlc_mode()
3247 		clear_reg_bits(info, CHA + CCR0, BIT6);  in hdlc_mode()
3262 	clear_reg_bits(info, CHA + MODE, BIT3);  in rx_stop()
3279 	set_reg_bits(info, CHA + MODE, BIT3);  in rx_start()
3339 	write_reg(info, CHA + CCR0, 0x80);  in reset_device()
3341 	write_reg(info, CHA + MODE, 0);  in reset_device()
3345 	irq_disable(info, CHA, 0xffff);  in reset_device()
3391 	irq_disable(info, CHA, 0xffff);  in async_mode()
3415 	write_reg(info, CHA + MODE, val);  in async_mode()
3427 	write_reg(info, CHA + CCR0, 0x83);  in async_mode()
3438 	write_reg(info, CHA + CCR1, 0x1f);  in async_mode()
3452 	write_reg(info, CHA + CCR2, 0x10);  in async_mode()
3461 	write_reg(info, CHA + CCR3, 0);  in async_mode()
3473 	write_reg(info, CHA + CCR4, 0x50);  in async_mode()
3474 	mgslpc_set_rate(info, CHA, info->params.data_rate * 16);  in async_mode()
3499 	write_reg(info, CHA + DAFO, val);  in async_mode()
3513 	write_reg(info, CHA + RFC, 0x5c);  in async_mode()
3519 	write_reg(info, CHA + RLCR, 0);  in async_mode()
3534 	write_reg(info, CHA + XBCH, val);  in async_mode()
3536 		irq_enable(info, CHA, IRQ_CTS);  in async_mode()
3539 	set_reg_bits(info, CHA + MODE, BIT3);  in async_mode()
3544 		set_reg_bits(info, CHA + PVR, BIT3);  in async_mode()
3546 		clear_reg_bits(info, CHA + PVR, BIT3);  in async_mode()
3547 	irq_enable(info, CHA,  in async_mode()
3550 	issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);  in async_mode()
3551 	wait_command_complete(info, CHA);  in async_mode()
3552 	read_reg16(info, CHA + ISR);	/* clear pending IRQs */  in async_mode()
3561 		set_reg_bits(info, CHA + CCR1, BIT3);  in tx_set_idle()
3563 		clear_reg_bits(info, CHA + CCR1, BIT3);  in tx_set_idle()
3580 	status = read_reg(info, CHA + PVR);  in get_signals()
3594 	val = read_reg(info, CHA + MODE);  in set_signals()
3606 	write_reg(info, CHA + MODE, val);  in set_signals()
3609 		clear_reg_bits(info, CHA + PVR, PVR_DTR);  in set_signals()
3611 		set_reg_bits(info, CHA + PVR, PVR_DTR);  in set_signals()
3758 	irq_enable(info, CHA, IRQ_TIMER);  in irq_test()
3759 	write_reg(info, CHA + TIMR, 0);	/* 512 cycles */  in irq_test()
3760 	issue_command(info, CHA, CMD_START_TIMER);  in irq_test()