102 	NV_ADMA_CTL			= 0x40,  enumerator
609 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_register_mode()
610 	writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);  in nv_adma_register_mode()
639 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_mode()
640 	writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);  in nv_adma_mode()
1021 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_freeze()
1023 		mmio + NV_ADMA_CTL);  in nv_adma_freeze()
1024 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_freeze()
1039 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_thaw()
1041 		mmio + NV_ADMA_CTL);  in nv_adma_thaw()
1042 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_thaw()
1168 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1170 		NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1172 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1173 	writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1174 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_port_start()
1176 	writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1177 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_port_start()
1188 	writew(0, mmio + NV_ADMA_CTL);  in nv_adma_port_stop()
1204 	writew(0, mmio + NV_ADMA_CTL);  in nv_adma_port_suspend()
1229 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1231 		NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1233 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1234 	writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1235 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_port_resume()
1237 	writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1238 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_port_resume()
1679 		tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_error_handler()
1680 		writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_error_handler()
1681 		readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_error_handler()
1683 		writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_error_handler()
1684 		readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_error_handler()