856 static inline void writelfl(unsigned long data, void __iomem *addr)  in writelfl()  function
980 				writelfl(new, addr); /* read after write */  in mv_write_cached_reg()
1002 	writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,  in mv_set_edma_ptrs()
1004 	writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);  in mv_set_edma_ptrs()
1014 	writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);  in mv_set_edma_ptrs()
1015 	writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,  in mv_set_edma_ptrs()
1033 	writelfl(mask, hpriv->main_irq_mask_addr);  in mv_write_main_irq_mask()
1074 	writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);  in mv_clear_and_enable_port_irqs()
1078 	writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);  in mv_clear_and_enable_port_irqs()
1082 		writelfl(0, port_mmio + FIS_IRQ_CAUSE);  in mv_clear_and_enable_port_irqs()
1178 		writelfl(EDMA_EN, port_mmio + EDMA_CMD);  in mv_start_edma()
1218 	writelfl(EDMA_DS, port_mmio + EDMA_CMD);  in mv_stop_edma_engine()
1396 				writelfl(lp_phy_val, lp_phy_addr);  in mv_scr_write()
1399 		writelfl(val, addr);  in mv_scr_write()
1662 	writelfl(cfg, port_mmio + EDMA_CFG);  in mv_edma_cfg()
1895 	writelfl(pp->sg_tbl_dma[qc->hw_tag],  in mv_bmdma_setup()
1917 	writelfl(cmd, port_mmio + BMDMA_CMD);  in mv_bmdma_start()
1938 		writelfl(cmd, port_mmio + BMDMA_CMD);  in mv_bmdma_stop_ap()
2236 	writelfl(ifctl, port_mmio + SATA_IFCTL);  in mv_send_fis()
2243 	writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);  in mv_send_fis()
2244 	writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);  in mv_send_fis()
2255 	writelfl(old_ifctl, port_mmio + SATA_IFCTL);  in mv_send_fis()
2357 		writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,  in mv_qc_issue()
2659 		writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);  in mv_err_intr()
2661 	writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);  in mv_err_intr()
2835 		writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |  in mv_process_crpb_entries()
2935 			writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);  in mv_host_intr()
2964 	writelfl(0, mmio + hpriv->irq_cause_offset);  in mv_pci_error()
3077 		writelfl(val, addr + ofs);  in mv5_scr_write()
3556 	writelfl(ifcfg, port_mmio + SATA_IFCFG);  in mv_setup_ifcfg()
3570 	writelfl(EDMA_RESET, port_mmio + EDMA_CMD);  in mv_reset_channel()
3581 	writelfl(EDMA_RESET, port_mmio + EDMA_CMD);  in mv_reset_channel()
3583 	writelfl(0, port_mmio + EDMA_CMD);  in mv_reset_channel()
3600 			writelfl(reg, port_mmio + SATA_IFCTL);  in mv_pmp_select()
3679 	writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);  in mv_eh_thaw()
3717 	writelfl(readl(serr), serr);  in mv_port_init()
3718 	writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);  in mv_port_init()
3721 	writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);  in mv_port_init()
3765 		writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);  in mv_60x1b2_errata_pci7()
3977 		writelfl(0, hc_mmio + HC_IRQ_CAUSE);  in mv_init_host()
3982 		writelfl(0, mmio + hpriv->irq_cause_offset);  in mv_init_host()
3985 		writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);  in mv_init_host()