637 static int mv_stop_edma_engine(void __iomem *port_mmio);
944 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_save_cached_regs()  local
947 	pp->cached.fiscfg = readl(port_mmio + FISCFG);  in mv_save_cached_regs()
948 	pp->cached.ltmode = readl(port_mmio + LTMODE);  in mv_save_cached_regs()
949 	pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);  in mv_save_cached_regs()
950 	pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);  in mv_save_cached_regs()
988 static void mv_set_edma_ptrs(void __iomem *port_mmio,  in mv_set_edma_ptrs()  argument
1001 	writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);  in mv_set_edma_ptrs()
1003 		 port_mmio + EDMA_REQ_Q_IN_PTR);  in mv_set_edma_ptrs()
1004 	writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);  in mv_set_edma_ptrs()
1013 	writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);  in mv_set_edma_ptrs()
1014 	writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);  in mv_set_edma_ptrs()
1016 		 port_mmio + EDMA_RSP_Q_OUT_PTR);  in mv_set_edma_ptrs()
1064 					  void __iomem *port_mmio,  in mv_clear_and_enable_port_irqs()  argument
1074 	writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);  in mv_clear_and_enable_port_irqs()
1082 		writelfl(0, port_mmio + FIS_IRQ_CAUSE);  in mv_clear_and_enable_port_irqs()
1160 static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,  in mv_start_edma()  argument
1175 		mv_set_edma_ptrs(port_mmio, hpriv, pp);  in mv_start_edma()
1176 		mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);  in mv_start_edma()
1178 		writelfl(EDMA_EN, port_mmio + EDMA_CMD);  in mv_start_edma()
1185 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_wait_for_edma_empty_idle()  local
1198 		u32 edma_stat = readl(port_mmio + EDMA_STATUS);  in mv_wait_for_edma_empty_idle()
1213 static int mv_stop_edma_engine(void __iomem *port_mmio)  in mv_stop_edma_engine()  argument
1218 	writelfl(EDMA_DS, port_mmio + EDMA_CMD);  in mv_stop_edma_engine()
1222 		u32 reg = readl(port_mmio + EDMA_CMD);  in mv_stop_edma_engine()
1232 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_stop_edma()  local
1240 	if (mv_stop_edma_engine(port_mmio)) {  in mv_stop_edma()
1481 	void __iomem *port_mmio;  in mv_config_fbs()  local
1501 	port_mmio = mv_ap_base(ap);  in mv_config_fbs()
1502 	mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);  in mv_config_fbs()
1503 	mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);  in mv_config_fbs()
1504 	mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);  in mv_config_fbs()
1606 	void __iomem *port_mmio    = mv_ap_base(ap);  in mv_edma_cfg()  local
1662 	writelfl(cfg, port_mmio + EDMA_CFG);  in mv_edma_cfg()
1884 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_bmdma_setup()  local
1890 	writel(0, port_mmio + BMDMA_CMD);  in mv_bmdma_setup()
1894 		port_mmio + BMDMA_PRD_HIGH);  in mv_bmdma_setup()
1896 		port_mmio + BMDMA_PRD_LOW);  in mv_bmdma_setup()
1912 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_bmdma_start()  local
1917 	writelfl(cmd, port_mmio + BMDMA_CMD);  in mv_bmdma_start()
1931 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_bmdma_stop_ap()  local
1935 	cmd = readl(port_mmio + BMDMA_CMD);  in mv_bmdma_stop_ap()
1938 		writelfl(cmd, port_mmio + BMDMA_CMD);  in mv_bmdma_stop_ap()
1961 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_bmdma_status()  local
1968 	reg = readl(port_mmio + BMDMA_STATUS);  in mv_bmdma_status()
2229 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_send_fis()  local
2234 	old_ifctl = readl(port_mmio + SATA_IFCTL);  in mv_send_fis()
2236 	writelfl(ifctl, port_mmio + SATA_IFCTL);  in mv_send_fis()
2240 		writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);  in mv_send_fis()
2243 	writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);  in mv_send_fis()
2244 	writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);  in mv_send_fis()
2251 		ifstat = readl(port_mmio + SATA_IFSTAT);  in mv_send_fis()
2255 	writelfl(old_ifctl, port_mmio + SATA_IFCTL);  in mv_send_fis()
2336 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_qc_issue()  local
2352 		mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);  in mv_qc_issue()
2358 					port_mmio + EDMA_REQ_Q_IN_PTR);  in mv_qc_issue()
2463 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_get_err_pmp_map()  local
2465 	return readl(port_mmio + SATA_TESTCTL) >> 16;  in mv_get_err_pmp_map()
2493 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_req_q_empty()  local
2496 	in_ptr  = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)  in mv_req_q_empty()
2498 	out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)  in mv_req_q_empty()
2638 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_err_intr()  local
2656 	edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);  in mv_err_intr()
2658 		fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);  in mv_err_intr()
2659 		writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);  in mv_err_intr()
2661 	writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);  in mv_err_intr()
2801 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_process_crpb_entries()  local
2809 	in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)  in mv_process_crpb_entries()
2837 			 port_mmio + EDMA_RSP_Q_OUT_PTR);  in mv_process_crpb_entries()
3157 #define ZERO(reg) writel(0, port_mmio + (reg))
3161 	void __iomem *port_mmio = mv_port_base(mmio, port);  in mv5_reset_hc_port()  local
3166 	writel(0x11f, port_mmio + EDMA_CFG);  in mv5_reset_hc_port()
3177 	writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);  in mv5_reset_hc_port()
3319 	void __iomem *port_mmio;  in mv6_read_preamp()  local
3329 	port_mmio = mv_port_base(mmio, idx);  in mv6_read_preamp()
3330 	tmp = readl(port_mmio + PHY_MODE2);  in mv6_read_preamp()
3344 	void __iomem *port_mmio = mv_port_base(mmio, port);  in mv6_phy_errata()  local
3354 		m2 = readl(port_mmio + PHY_MODE2);  in mv6_phy_errata()
3357 		writel(m2, port_mmio + PHY_MODE2);  in mv6_phy_errata()
3361 		m2 = readl(port_mmio + PHY_MODE2);  in mv6_phy_errata()
3363 		writel(m2, port_mmio + PHY_MODE2);  in mv6_phy_errata()
3372 	m3 = readl(port_mmio + PHY_MODE3);  in mv6_phy_errata()
3380 		u32 m4 = readl(port_mmio + PHY_MODE4);  in mv6_phy_errata()
3390 		writel(m4, port_mmio + PHY_MODE4);  in mv6_phy_errata()
3398 	writel(m3, port_mmio + PHY_MODE3);  in mv6_phy_errata()
3401 	m2 = readl(port_mmio + PHY_MODE2);  in mv6_phy_errata()
3414 	writel(m2, port_mmio + PHY_MODE2);  in mv6_phy_errata()
3428 	void __iomem *port_mmio;  in mv_soc_read_preamp()  local
3431 	port_mmio = mv_port_base(mmio, idx);  in mv_soc_read_preamp()
3432 	tmp = readl(port_mmio + PHY_MODE2);  in mv_soc_read_preamp()
3439 #define ZERO(reg) writel(0, port_mmio + (reg))
3443 	void __iomem *port_mmio = mv_port_base(mmio, port);  in mv_soc_reset_hc_port()  local
3448 	writel(0x101f, port_mmio + EDMA_CFG);  in mv_soc_reset_hc_port()
3459 	writel(0x800, port_mmio + EDMA_IORDY_TMOUT);  in mv_soc_reset_hc_port()
3505 	void __iomem *port_mmio = mv_port_base(mmio, port);  in mv_soc_65n_phy_errata()  local
3508 	reg = readl(port_mmio + PHY_MODE3);  in mv_soc_65n_phy_errata()
3513 	writel(reg, port_mmio + PHY_MODE3);  in mv_soc_65n_phy_errata()
3515 	reg = readl(port_mmio + PHY_MODE4);  in mv_soc_65n_phy_errata()
3518 	writel(reg, port_mmio + PHY_MODE4);  in mv_soc_65n_phy_errata()
3520 	reg = readl(port_mmio + PHY_MODE9_GEN2);  in mv_soc_65n_phy_errata()
3524 	writel(reg, port_mmio + PHY_MODE9_GEN2);  in mv_soc_65n_phy_errata()
3526 	reg = readl(port_mmio + PHY_MODE9_GEN1);  in mv_soc_65n_phy_errata()
3530 	writel(reg, port_mmio + PHY_MODE9_GEN1);  in mv_soc_65n_phy_errata()
3549 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)  in mv_setup_ifcfg()  argument
3551 	u32 ifcfg = readl(port_mmio + SATA_IFCFG);  in mv_setup_ifcfg()
3556 	writelfl(ifcfg, port_mmio + SATA_IFCFG);  in mv_setup_ifcfg()
3562 	void __iomem *port_mmio = mv_port_base(mmio, port_no);  in mv_reset_channel()  local
3569 	mv_stop_edma_engine(port_mmio);  in mv_reset_channel()
3570 	writelfl(EDMA_RESET, port_mmio + EDMA_CMD);  in mv_reset_channel()
3574 		mv_setup_ifcfg(port_mmio, 1);  in mv_reset_channel()
3581 	writelfl(EDMA_RESET, port_mmio + EDMA_CMD);  in mv_reset_channel()
3583 	writelfl(0, port_mmio + EDMA_CMD);  in mv_reset_channel()
3594 		void __iomem *port_mmio = mv_ap_base(ap);  in mv_pmp_select()  local
3595 		u32 reg = readl(port_mmio + SATA_IFCTL);  in mv_pmp_select()
3600 			writelfl(reg, port_mmio + SATA_IFCTL);  in mv_pmp_select()
3671 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_eh_thaw()  local
3675 	writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);  in mv_eh_thaw()
3696 static void mv_port_init(struct ata_ioports *port,  void __iomem *port_mmio)  in mv_port_init()  argument
3698 	void __iomem *serr, *shd_base = port_mmio + SHD_BLK;  in mv_port_init()
3716 	serr = port_mmio + mv_scr_offset(SCR_ERROR);  in mv_port_init()
3718 	writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);  in mv_port_init()
3721 	writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);  in mv_port_init()
3724 		readl(port_mmio + EDMA_CFG),  in mv_port_init()
3725 		readl(port_mmio + EDMA_ERR_IRQ_CAUSE),  in mv_port_init()
3726 		readl(port_mmio + EDMA_ERR_IRQ_MASK));  in mv_port_init()
3963 		void __iomem *port_mmio = mv_port_base(mmio, port);  in mv_init_host()  local
3965 		mv_port_init(&ap->ioaddr, port_mmio);  in mv_init_host()
4419 		void __iomem *port_mmio = mv_port_base(hpriv->base, port);  in mv_pci_init_one()  local
4420 		unsigned int offset = port_mmio - hpriv->base;  in mv_pci_init_one()