438 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)  argument
439 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)  argument
440 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)  argument
441 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)  argument
442 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)  argument
577 	void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
579 	void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
580 	void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
582 	int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
584 	void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
604 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
606 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
607 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
609 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
611 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
614 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
616 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
617 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
619 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
621 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
622 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
624 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
626 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
628 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
631 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
634 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
918 	struct mv_host_priv *hpriv = host->private_data;  in mv_host_base()  local
919 	return hpriv->base;  in mv_host_base()
989 			     struct mv_host_priv *hpriv,  in mv_set_edma_ptrs()  argument
1019 static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)  in mv_write_main_irq_mask()  argument
1033 	writelfl(mask, hpriv->main_irq_mask_addr);  in mv_write_main_irq_mask()
1039 	struct mv_host_priv *hpriv = host->private_data;  in mv_set_main_irq_mask()  local
1042 	old_mask = hpriv->main_irq_mask;  in mv_set_main_irq_mask()
1045 		hpriv->main_irq_mask = new_mask;  in mv_set_main_irq_mask()
1046 		mv_write_main_irq_mask(new_mask, hpriv);  in mv_set_main_irq_mask()
1067 	struct mv_host_priv *hpriv = ap->host->private_data;  in mv_clear_and_enable_port_irqs()  local
1081 	if (IS_GEN_IIE(hpriv))  in mv_clear_and_enable_port_irqs()
1090 	struct mv_host_priv *hpriv = host->private_data;  in mv_set_irq_coalescing()  local
1091 	void __iomem *mmio = hpriv->base, *hc_mmio;  in mv_set_irq_coalescing()
1094 	unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;  in mv_set_irq_coalescing()
1113 	if (is_dual_hc && !IS_GEN_I(hpriv)) {  in mv_set_irq_coalescing()
1171 		struct mv_host_priv *hpriv = ap->host->private_data;  in mv_start_edma()  local
1175 		mv_set_edma_ptrs(port_mmio, hpriv, pp);  in mv_start_edma()
1362 		struct mv_host_priv *hpriv = link->ap->host->private_data;  in mv_scr_write()  local
1380 			if (hpriv->hp_flags & MV_HP_FIX_LP_PHY_CTL) {  in mv_scr_write()
1509 	struct mv_host_priv *hpriv = ap->host->private_data;  in mv_60x1_errata_sata25()  local
1513 	old = readl(hpriv->base + GPIO_PORT_CTL);  in mv_60x1_errata_sata25()
1519 		writel(new, hpriv->base + GPIO_PORT_CTL);  in mv_60x1_errata_sata25()
1563 	struct mv_host_priv *hpriv = host->private_data;  in mv_soc_led_blink_enable()  local
1567 	if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)  in mv_soc_led_blink_enable()
1569 	hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;  in mv_soc_led_blink_enable()
1578 	struct mv_host_priv *hpriv = host->private_data;  in mv_soc_led_blink_disable()  local
1583 	if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))  in mv_soc_led_blink_disable()
1587 	for (port = 0; port < hpriv->n_ports; port++) {  in mv_soc_led_blink_disable()
1595 	hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;  in mv_soc_led_blink_disable()
1605 	struct mv_host_priv *hpriv = ap->host->private_data;  in mv_edma_cfg()  local
1613 	if (IS_GEN_I(hpriv))  in mv_edma_cfg()
1616 	else if (IS_GEN_II(hpriv)) {  in mv_edma_cfg()
1620 	} else if (IS_GEN_IIE(hpriv)) {  in mv_edma_cfg()
1642 			if (!IS_SOC(hpriv))  in mv_edma_cfg()
1645 		if (hpriv->hp_flags & MV_HP_CUT_THROUGH)  in mv_edma_cfg()
1649 		if (IS_SOC(hpriv)) {  in mv_edma_cfg()
1667 	struct mv_host_priv *hpriv = ap->host->private_data;  in mv_port_free_dma_mem()  local
1672 		dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);  in mv_port_free_dma_mem()
1676 		dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);  in mv_port_free_dma_mem()
1685 			if (tag == 0 || !IS_GEN_I(hpriv))  in mv_port_free_dma_mem()
1686 				dma_pool_free(hpriv->sg_tbl_pool,  in mv_port_free_dma_mem()
1707 	struct mv_host_priv *hpriv = ap->host->private_data;  in mv_port_start()  local
1717 	pp->crqb = dma_pool_zalloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);  in mv_port_start()
1721 	pp->crpb = dma_pool_zalloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);  in mv_port_start()
1726 	if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)  in mv_port_start()
1733 		if (tag == 0 || !IS_GEN_I(hpriv)) {  in mv_port_start()
1734 			pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,  in mv_port_start()
2403 		struct mv_host_priv *hpriv = ap->host->private_data;  in mv_qc_issue()  local
2415 		if (IS_GEN_II(hpriv))  in mv_qc_issue()
2642 	struct mv_host_priv *hpriv = ap->host->private_data;  in mv_err_intr()  local
2657 	if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {  in mv_err_intr()
2677 	if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {  in mv_err_intr()
2714 	if (IS_GEN_I(hpriv)) {  in mv_err_intr()
2802 	struct mv_host_priv *hpriv = ap->host->private_data;  in mv_process_crpb_entries()  local
2819 		if (IS_GEN_I(hpriv)) {  in mv_process_crpb_entries()
2885 	struct mv_host_priv *hpriv = host->private_data;  in mv_host_intr()  local
2886 	void __iomem *mmio = hpriv->base, *hc_mmio;  in mv_host_intr()
2893 	for (port = 0; port < hpriv->n_ports; port++) {  in mv_host_intr()
2928 				if ((port + p) >= hpriv->n_ports)  in mv_host_intr()
2950 	struct mv_host_priv *hpriv = host->private_data;  in mv_pci_error()  local
2957 	err_cause = readl(mmio + hpriv->irq_cause_offset);  in mv_pci_error()
2964 	writelfl(0, mmio + hpriv->irq_cause_offset);  in mv_pci_error()
3005 	struct mv_host_priv *hpriv = host->private_data;  in mv_interrupt()  local
3007 	int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;  in mv_interrupt()
3014 		mv_write_main_irq_mask(0, hpriv);  in mv_interrupt()
3016 	main_irq_cause = readl(hpriv->main_irq_cause_addr);  in mv_interrupt()
3017 	pending_irqs   = main_irq_cause & hpriv->main_irq_mask;  in mv_interrupt()
3023 		if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))  in mv_interrupt()
3024 			handled = mv_pci_error(host, hpriv->base);  in mv_interrupt()
3031 		mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);  in mv_interrupt()
3057 	struct mv_host_priv *hpriv = link->ap->host->private_data;  in mv5_scr_read()  local
3058 	void __iomem *mmio = hpriv->base;  in mv5_scr_read()
3071 	struct mv_host_priv *hpriv = link->ap->host->private_data;  in mv5_scr_write()  local
3072 	void __iomem *mmio = hpriv->base;  in mv5_scr_write()
3099 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)  in mv5_reset_flash()  argument
3104 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,  in mv5_read_preamp()  argument
3112 	hpriv->signal[idx].pre = tmp & 0x1800;	/* bits 12:11 */  in mv5_read_preamp()
3113 	hpriv->signal[idx].amps = tmp & 0xe0;	/* bits 7:5 */  in mv5_read_preamp()
3116 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)  in mv5_enable_leds()  argument
3129 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,  in mv5_phy_errata()  argument
3135 	int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);  in mv5_phy_errata()
3150 	tmp |= hpriv->signal[port].pre;  in mv5_phy_errata()
3151 	tmp |= hpriv->signal[port].amps;  in mv5_phy_errata()
3158 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,  in mv5_reset_hc_port()  argument
3163 	mv_reset_channel(hpriv, mmio, port);  in mv5_reset_hc_port()
3182 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,  in mv5_reset_one_hc()  argument
3200 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,  in mv5_reset_hc()  argument
3207 			mv5_reset_hc_port(hpriv, mmio,  in mv5_reset_hc()
3210 		mv5_reset_one_hc(hpriv, mmio, hc);  in mv5_reset_hc()
3220 	struct mv_host_priv *hpriv = host->private_data;  in mv_reset_pci_bus()  local
3231 	ZERO(hpriv->irq_cause_offset);  in mv_reset_pci_bus()
3232 	ZERO(hpriv->irq_mask_offset);  in mv_reset_pci_bus()
3240 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)  in mv6_reset_flash()  argument
3244 	mv5_reset_flash(hpriv, mmio);  in mv6_reset_flash()
3261 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,  in mv6_reset_hc()  argument
3316 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,  in mv6_read_preamp()  argument
3324 		hpriv->signal[idx].amps = 0x7 << 8;  in mv6_read_preamp()
3325 		hpriv->signal[idx].pre = 0x1 << 5;  in mv6_read_preamp()
3332 	hpriv->signal[idx].amps = tmp & 0x700;	/* bits 10:8 */  in mv6_read_preamp()
3333 	hpriv->signal[idx].pre = tmp & 0xe0;	/* bits 7:5 */  in mv6_read_preamp()
3336 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)  in mv6_enable_leds()  argument
3341 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,  in mv6_phy_errata()  argument
3346 	u32 hp_flags = hpriv->hp_flags;  in mv6_phy_errata()
3376 	if (IS_SOC(hpriv))  in mv6_phy_errata()
3386 		if (IS_GEN_IIE(hpriv))  in mv6_phy_errata()
3404 	m2 |= hpriv->signal[port].amps;  in mv6_phy_errata()
3405 	m2 |= hpriv->signal[port].pre;  in mv6_phy_errata()
3409 	if (IS_GEN_IIE(hpriv)) {  in mv6_phy_errata()
3419 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,  in mv_soc_enable_leds()  argument
3425 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,  in mv_soc_read_preamp()  argument
3434 	hpriv->signal[idx].amps = tmp & 0x700;	/* bits 10:8 */  in mv_soc_read_preamp()
3435 	hpriv->signal[idx].pre = tmp & 0xe0;	/* bits 7:5 */  in mv_soc_read_preamp()
3440 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,  in mv_soc_reset_hc_port()  argument
3445 	mv_reset_channel(hpriv, mmio, port);  in mv_soc_reset_hc_port()
3465 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,  in mv_soc_reset_one_hc()  argument
3478 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,  in mv_soc_reset_hc()  argument
3483 	for (port = 0; port < hpriv->n_ports; port++)  in mv_soc_reset_hc()
3484 		mv_soc_reset_hc_port(hpriv, mmio, port);  in mv_soc_reset_hc()
3486 	mv_soc_reset_one_hc(hpriv, mmio);  in mv_soc_reset_hc()
3491 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,  in mv_soc_reset_flash()  argument
3502 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,  in mv_soc_65n_phy_errata()  argument
3540 static bool soc_is_65n(struct mv_host_priv *hpriv)  in soc_is_65n()  argument
3542 	void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);  in soc_is_65n()
3559 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,  in mv_reset_channel()  argument
3572 	if (!IS_GEN_I(hpriv)) {  in mv_reset_channel()
3585 	hpriv->ops->phy_errata(hpriv, mmio, port_no);  in mv_reset_channel()
3587 	if (IS_GEN_I(hpriv))  in mv_reset_channel()
3623 	struct mv_host_priv *hpriv = ap->host->private_data;  in mv_hardreset()  local
3625 	void __iomem *mmio = hpriv->base;  in mv_hardreset()
3630 	mv_reset_channel(hpriv, mmio, ap->port_no);  in mv_hardreset()
3646 		if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {  in mv_hardreset()
3667 	struct mv_host_priv *hpriv = ap->host->private_data;  in mv_eh_thaw()  local
3670 	void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);  in mv_eh_thaw()
3731 	struct mv_host_priv *hpriv = host->private_data;  in mv_in_pcix_mode()  local
3732 	void __iomem *mmio = hpriv->base;  in mv_in_pcix_mode()
3735 	if (IS_SOC(hpriv) || !IS_PCIE(hpriv))  in mv_in_pcix_mode()
3745 	struct mv_host_priv *hpriv = host->private_data;  in mv_pci_cut_through_okay()  local
3746 	void __iomem *mmio = hpriv->base;  in mv_pci_cut_through_okay()
3759 	struct mv_host_priv *hpriv = host->private_data;  in mv_60x1b2_errata_pci7()  local
3760 	void __iomem *mmio = hpriv->base;  in mv_60x1b2_errata_pci7()
3772 	struct mv_host_priv *hpriv = host->private_data;  in mv_chip_id()  local
3773 	u32 hp_flags = hpriv->hp_flags;  in mv_chip_id()
3777 		hpriv->ops = &mv5xxx_ops;  in mv_chip_id()
3797 		hpriv->ops = &mv5xxx_ops;  in mv_chip_id()
3817 		hpriv->ops = &mv6xxx_ops;  in mv_chip_id()
3869 		hpriv->ops = &mv6xxx_ops;  in mv_chip_id()
3886 		if (soc_is_65n(hpriv))  in mv_chip_id()
3887 			hpriv->ops = &mv_soc_65n_ops;  in mv_chip_id()
3889 			hpriv->ops = &mv_soc_ops;  in mv_chip_id()
3899 	hpriv->hp_flags = hp_flags;  in mv_chip_id()
3901 		hpriv->irq_cause_offset	= PCIE_IRQ_CAUSE;  in mv_chip_id()
3902 		hpriv->irq_mask_offset	= PCIE_IRQ_MASK;  in mv_chip_id()
3903 		hpriv->unmask_all_irqs	= PCIE_UNMASK_ALL_IRQS;  in mv_chip_id()
3905 		hpriv->irq_cause_offset	= PCI_IRQ_CAUSE;  in mv_chip_id()
3906 		hpriv->irq_mask_offset	= PCI_IRQ_MASK;  in mv_chip_id()
3907 		hpriv->unmask_all_irqs	= PCI_UNMASK_ALL_IRQS;  in mv_chip_id()
3926 	struct mv_host_priv *hpriv = host->private_data;  in mv_init_host()  local
3927 	void __iomem *mmio = hpriv->base;  in mv_init_host()
3929 	rc = mv_chip_id(host, hpriv->board_idx);  in mv_init_host()
3933 	if (IS_SOC(hpriv)) {  in mv_init_host()
3934 		hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;  in mv_init_host()
3935 		hpriv->main_irq_mask_addr  = mmio + SOC_HC_MAIN_IRQ_MASK;  in mv_init_host()
3937 		hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;  in mv_init_host()
3938 		hpriv->main_irq_mask_addr  = mmio + PCI_HC_MAIN_IRQ_MASK;  in mv_init_host()
3942 	hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);  in mv_init_host()
3950 		if (hpriv->ops->read_preamp)  in mv_init_host()
3951 			hpriv->ops->read_preamp(hpriv, port, mmio);  in mv_init_host()
3953 	rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);  in mv_init_host()
3957 	hpriv->ops->reset_flash(hpriv, mmio);  in mv_init_host()
3958 	hpriv->ops->reset_bus(host, mmio);  in mv_init_host()
3959 	hpriv->ops->enable_leds(hpriv, mmio);  in mv_init_host()
3980 	if (!IS_SOC(hpriv)) {  in mv_init_host()
3982 		writelfl(0, mmio + hpriv->irq_cause_offset);  in mv_init_host()
3985 		writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);  in mv_init_host()
3999 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)  in mv_create_dma_pools()  argument
4001 	hpriv->crqb_pool   = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,  in mv_create_dma_pools()
4003 	if (!hpriv->crqb_pool)  in mv_create_dma_pools()
4006 	hpriv->crpb_pool   = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,  in mv_create_dma_pools()
4008 	if (!hpriv->crpb_pool)  in mv_create_dma_pools()
4011 	hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,  in mv_create_dma_pools()
4013 	if (!hpriv->sg_tbl_pool)  in mv_create_dma_pools()
4019 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,  in mv_conf_mbus_windows()  argument
4025 		writel(0, hpriv->base + WINDOW_CTRL(i));  in mv_conf_mbus_windows()
4026 		writel(0, hpriv->base + WINDOW_BASE(i));  in mv_conf_mbus_windows()
4035 			hpriv->base + WINDOW_CTRL(i));  in mv_conf_mbus_windows()
4036 		writel(cs->base, hpriv->base + WINDOW_BASE(i));  in mv_conf_mbus_windows()
4055 	struct mv_host_priv *hpriv;  in mv_platform_probe()  local
4106 	hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);  in mv_platform_probe()
4108 	if (!host || !hpriv)  in mv_platform_probe()
4110 	hpriv->port_clks = devm_kcalloc(&pdev->dev,  in mv_platform_probe()
4113 	if (!hpriv->port_clks)  in mv_platform_probe()
4115 	hpriv->port_phys = devm_kcalloc(&pdev->dev,  in mv_platform_probe()
4118 	if (!hpriv->port_phys)  in mv_platform_probe()
4120 	host->private_data = hpriv;  in mv_platform_probe()
4121 	hpriv->board_idx = chip_soc;  in mv_platform_probe()
4124 	hpriv->base = devm_ioremap(&pdev->dev, res->start,  in mv_platform_probe()
4126 	if (!hpriv->base)  in mv_platform_probe()
4129 	hpriv->base -= SATAHC0_REG_BASE;  in mv_platform_probe()
4131 	hpriv->clk = clk_get(&pdev->dev, NULL);  in mv_platform_probe()
4132 	if (IS_ERR(hpriv->clk))  in mv_platform_probe()
4135 		clk_prepare_enable(hpriv->clk);  in mv_platform_probe()
4140 		hpriv->port_clks[port] = clk_get(&pdev->dev, port_number);  in mv_platform_probe()
4141 		if (!IS_ERR(hpriv->port_clks[port]))  in mv_platform_probe()
4142 			clk_prepare_enable(hpriv->port_clks[port]);  in mv_platform_probe()
4145 		hpriv->port_phys[port] = devm_phy_optional_get(&pdev->dev,  in mv_platform_probe()
4147 		if (IS_ERR(hpriv->port_phys[port])) {  in mv_platform_probe()
4148 			rc = PTR_ERR(hpriv->port_phys[port]);  in mv_platform_probe()
4149 			hpriv->port_phys[port] = NULL;  in mv_platform_probe()
4154 			hpriv->n_ports = port;  in mv_platform_probe()
4157 			phy_power_on(hpriv->port_phys[port]);  in mv_platform_probe()
4161 	hpriv->n_ports = n_ports;  in mv_platform_probe()
4168 		mv_conf_mbus_windows(hpriv, dram);  in mv_platform_probe()
4170 	rc = mv_create_dma_pools(hpriv, &pdev->dev);  in mv_platform_probe()
4181 		hpriv->hp_flags |= MV_HP_FIX_LP_PHY_CTL;  in mv_platform_probe()
4196 	if (!IS_ERR(hpriv->clk)) {  in mv_platform_probe()
4197 		clk_disable_unprepare(hpriv->clk);  in mv_platform_probe()
4198 		clk_put(hpriv->clk);  in mv_platform_probe()
4200 	for (port = 0; port < hpriv->n_ports; port++) {  in mv_platform_probe()
4201 		if (!IS_ERR(hpriv->port_clks[port])) {  in mv_platform_probe()
4202 			clk_disable_unprepare(hpriv->port_clks[port]);  in mv_platform_probe()
4203 			clk_put(hpriv->port_clks[port]);  in mv_platform_probe()
4205 		phy_power_off(hpriv->port_phys[port]);  in mv_platform_probe()
4222 	struct mv_host_priv *hpriv = host->private_data;  in mv_platform_remove()  local
4226 	if (!IS_ERR(hpriv->clk)) {  in mv_platform_remove()
4227 		clk_disable_unprepare(hpriv->clk);  in mv_platform_remove()
4228 		clk_put(hpriv->clk);  in mv_platform_remove()
4231 		if (!IS_ERR(hpriv->port_clks[port])) {  in mv_platform_remove()
4232 			clk_disable_unprepare(hpriv->port_clks[port]);  in mv_platform_remove()
4233 			clk_put(hpriv->port_clks[port]);  in mv_platform_remove()
4235 		phy_power_off(hpriv->port_phys[port]);  in mv_platform_remove()
4257 		struct mv_host_priv *hpriv = host->private_data;  in mv_platform_resume()  local
4264 			mv_conf_mbus_windows(hpriv, dram);  in mv_platform_resume()
4335 	struct mv_host_priv *hpriv = host->private_data;  in mv_print_info()  local
4350 	if (IS_GEN_I(hpriv))  in mv_print_info()
4352 	else if (IS_GEN_II(hpriv))  in mv_print_info()
4354 	else if (IS_GEN_IIE(hpriv))  in mv_print_info()
4361 		 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");  in mv_print_info()
4378 	struct mv_host_priv *hpriv;  in mv_pci_init_one()  local
4387 	hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);  in mv_pci_init_one()
4388 	if (!host || !hpriv)  in mv_pci_init_one()
4390 	host->private_data = hpriv;  in mv_pci_init_one()
4391 	hpriv->n_ports = n_ports;  in mv_pci_init_one()
4392 	hpriv->board_idx = board_idx;  in mv_pci_init_one()
4405 	hpriv->base = host->iomap[MV_PRIMARY_BAR];  in mv_pci_init_one()
4413 	rc = mv_create_dma_pools(hpriv, &pdev->dev);  in mv_pci_init_one()
4419 		void __iomem *port_mmio = mv_port_base(hpriv->base, port);  in mv_pci_init_one()
4420 		unsigned int offset = port_mmio - hpriv->base;  in mv_pci_init_one()
4433 		hpriv->hp_flags |= MV_HP_FLAG_MSI;  in mv_pci_init_one()
4441 				 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);  in mv_pci_init_one()