31 #define SCFG_OFFSET					0x1000  macro
203 	writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);  in tegra124_ahci_init()
206 		    SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);  in tegra124_ahci_init()
211 	writel(val, tegra->sata_regs + SCFG_OFFSET +  in tegra124_ahci_init()
215 		    SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);  in tegra124_ahci_init()
220 	writel(val, tegra->sata_regs + SCFG_OFFSET +  in tegra124_ahci_init()
224 	       tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);  in tegra124_ahci_init()
226 	       tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);  in tegra124_ahci_init()
228 	writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);  in tegra124_ahci_init()
317 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL17_0);  in tegra_ahci_controller_init()
319 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL18_0);  in tegra_ahci_controller_init()
321 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL20_0);  in tegra_ahci_controller_init()
323 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL21_0);  in tegra_ahci_controller_init()
327 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);  in tegra_ahci_controller_init()
330 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);  in tegra_ahci_controller_init()
332 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);  in tegra_ahci_controller_init()
339 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);  in tegra_ahci_controller_init()
344 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);  in tegra_ahci_controller_init()
347 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);  in tegra_ahci_controller_init()
356 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);  in tegra_ahci_controller_init()
359 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);  in tegra_ahci_controller_init()
361 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);  in tegra_ahci_controller_init()
364 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);  in tegra_ahci_controller_init()
366 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);  in tegra_ahci_controller_init()
368 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);  in tegra_ahci_controller_init()
373 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);  in tegra_ahci_controller_init()
375 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);  in tegra_ahci_controller_init()
377 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);  in tegra_ahci_controller_init()
380 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);  in tegra_ahci_controller_init()
385 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);  in tegra_ahci_controller_init()
391 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);  in tegra_ahci_controller_init()
394 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);  in tegra_ahci_controller_init()
397 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_IDP1);  in tegra_ahci_controller_init()
399 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);  in tegra_ahci_controller_init()
402 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);  in tegra_ahci_controller_init()