Lines Matching +full:0 +full:x40020000
27 #define SATA_CONFIGURATION_0 0x180
28 #define SATA_CONFIGURATION_0_EN_FPCI BIT(0)
31 #define SCFG_OFFSET 0x1000
33 #define T_SATA0_CFG_1 0x04
34 #define T_SATA0_CFG_1_IO_SPACE BIT(0)
39 #define T_SATA0_CFG_9 0x24
40 #define T_SATA0_CFG_9_BASE_ADDRESS 0x40020000
42 #define SATA_FPCI_BAR5 0x94
43 #define SATA_FPCI_BAR5_START_MASK (0xfffffff << 4)
44 #define SATA_FPCI_BAR5_START (0x0040020 << 4)
45 #define SATA_FPCI_BAR5_ACCESS_TYPE (0x1)
47 #define SATA_INTR_MASK 0x188
50 #define T_SATA0_CFG_35 0x94
51 #define T_SATA0_CFG_35_IDP_INDEX_MASK (0x7ff << 2)
52 #define T_SATA0_CFG_35_IDP_INDEX (0x2a << 2)
54 #define T_SATA0_AHCI_IDP1 0x98
55 #define T_SATA0_AHCI_IDP1_DATA (0x400040)
57 #define T_SATA0_CFG_PHY_1 0x12c
61 #define T_SATA0_NVOOB 0x114
62 #define T_SATA0_NVOOB_COMMA_CNT_MASK (0xff << 16)
63 #define T_SATA0_NVOOB_COMMA_CNT (0x07 << 16)
64 #define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK (0x3 << 24)
65 #define T_SATA0_NVOOB_SQUELCH_FILTER_MODE (0x1 << 24)
66 #define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK (0x3 << 26)
67 #define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH (0x3 << 26)
69 #define T_SATA_CFG_PHY_0 0x120
73 #define T_SATA0_CFG2NVOOB_2 0x134
74 #define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK (0x1ff << 18)
75 #define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW (0xc << 18)
77 #define T_SATA0_AHCI_HBA_CAP_BKDR 0x300
84 #define T_SATA0_BKDOOR_CC 0x4a4
85 #define T_SATA0_BKDOOR_CC_CLASS_CODE_MASK (0xffff << 16)
86 #define T_SATA0_BKDOOR_CC_CLASS_CODE (0x0106 << 16)
87 #define T_SATA0_BKDOOR_CC_PROG_IF_MASK (0xff << 8)
88 #define T_SATA0_BKDOOR_CC_PROG_IF (0x01 << 8)
90 #define T_SATA0_CFG_SATA 0x54c
93 #define T_SATA0_CFG_MISC 0x550
95 #define T_SATA0_INDEX 0x680
97 #define T_SATA0_CHX_PHY_CTRL1_GEN1 0x690
98 #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK 0xff
99 #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT 0
100 #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK (0xff << 8)
103 #define T_SATA0_CHX_PHY_CTRL1_GEN2 0x694
104 #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK 0xff
105 #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT 0
106 #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK (0xff << 12)
109 #define T_SATA0_CHX_PHY_CTRL2 0x69c
110 #define T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1 0x23
112 #define T_SATA0_CHX_PHY_CTRL11 0x6d0
113 #define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16)
115 #define T_SATA0_CHX_PHY_CTRL17_0 0x6e8
116 #define T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1 0x55010000
117 #define T_SATA0_CHX_PHY_CTRL18_0 0x6ec
118 #define T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2 0x55010000
119 #define T_SATA0_CHX_PHY_CTRL20_0 0x6f4
120 #define T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1 0x1
121 #define T_SATA0_CHX_PHY_CTRL21_0 0x6f8
122 #define T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2 0x1
125 #define SATA_AUX_MISC_CNTL_1_0 0x8
130 #define SATA_AUX_RX_STAT_INT_0 0xc
133 #define SATA_AUX_SPARE_CFG0_0 0x18
136 #define FUSE_SATA_CALIB 0x124
137 #define FUSE_SATA_CALIB_MASK 0x3
147 {0x18, 0x04, 0x18, 0x0a},
148 {0x0e, 0x04, 0x14, 0x0a},
149 {0x0e, 0x07, 0x1a, 0x0e},
150 {0x14, 0x0e, 0x1a, 0x0e},
203 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); in tegra124_ahci_init()
228 writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); in tegra124_ahci_init()
230 return 0; in tegra124_ahci_init()
259 return 0; in tegra_ahci_power_on()
417 return 0; in tegra_ahci_controller_init()
487 hpriv = ahci_platform_get_resources(pdev, 0); in tegra_ahci_probe()
566 return 0; in tegra_ahci_probe()