Lines Matching +full:way +full:- +full:select
1 # SPDX-License-Identifier: GPL-2.0
4 select ARCH_32BIT_OFF_T
5 select ARCH_HAS_BINFMT_FLAT if !MMU
6 select ARCH_HAS_DMA_PREP_COHERENT if MMU
7 select ARCH_HAS_SYNC_DMA_FOR_CPU if MMU
8 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if MMU
9 select ARCH_HAS_DMA_SET_UNCACHED if MMU
10 select ARCH_USE_QUEUED_RWLOCKS
11 select ARCH_USE_QUEUED_SPINLOCKS
12 select ARCH_WANT_FRAME_POINTERS
13 select ARCH_WANT_IPC_PARSE_VERSION
14 select BUILDTIME_TABLE_SORT
15 select CLONE_BACKWARDS
16 select COMMON_CLK
17 select DMA_REMAP if MMU
18 select GENERIC_ATOMIC64
19 select GENERIC_CLOCKEVENTS
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_STRNCPY_FROM_USER if KASAN
24 select HAVE_ARCH_AUDITSYSCALL
25 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
26 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
27 select HAVE_ARCH_SECCOMP_FILTER
28 select HAVE_ARCH_TRACEHOOK
29 select HAVE_DEBUG_KMEMLEAK
30 select HAVE_DMA_CONTIGUOUS
31 select HAVE_EXIT_THREAD
32 select HAVE_FUNCTION_TRACER
33 select HAVE_FUTEX_CMPXCHG if !MMU && FUTEX
34 select HAVE_HW_BREAKPOINT if PERF_EVENTS
35 select HAVE_IRQ_TIME_ACCOUNTING
36 select HAVE_OPROFILE
37 select HAVE_PCI
38 select HAVE_PERF_EVENTS
39 select HAVE_STACKPROTECTOR
40 select HAVE_SYSCALL_TRACEPOINTS
41 select IRQ_DOMAIN
42 select MODULES_USE_ELF_RELA
43 select PERF_USE_VMALLOC
44 select SET_FS
45 select VIRT_TO_BUS
47 Xtensa processors are 32-bit RISC machines designed by Tensilica
52 a home page at <http://www.linux-xtensa.org/>.
96 bool "fsf - default (not generic) configuration"
97 select MMU
100 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
101 select MMU
102 select HAVE_XTENSA_GPIO32
107 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
108 select MMU
109 select HAVE_XTENSA_GPIO32
115 select HAVE_XTENSA_GPIO32
117 Select this variant to use a custom Xtensa processor configuration.
127 Don't forget you have to select MMU if you have one.
140 select MMU
143 ie: it supports a TLB with auto-loading, page protection.
183 select XTENSA_MX
185 This option is used to indicate that the system-on-a-chip (SOC)
196 You still have to select "Enable SMP" to enable SMP on this SOC.
199 bool "Enable Symmetric multi-processing support"
201 select GENERIC_SMP_IDLE_THREAD
208 int "Maximum number of CPUs (2-32)"
254 Select supported userspace ABI.
267 select USER_ABI_CALL0
269 Select this option to support only call0 ABI in userspace.
278 select USER_ABI_CALL0
280 Select this option to support both windowed and call0 userspace
318 select XTENSA_CALIBRATE_CCOUNT
319 select SERIAL_CONSOLE
325 select HAVE_IDE
327 XT2000 is the name of Tensilica's feature-rich emulation platform.
332 select ETHOC if ETHERNET
333 select PLATFORM_WANT_DEFAULT_MEM if !MMU
334 select SERIAL_CONSOLE
335 select XTENSA_CALIBRATE_CCOUNT
336 select PLATFORM_HAVE_XIP
366 On some architectures (EBSA110 and CATS), there is currently no way
368 architectures, you should supply some command-line options at build
374 select OF
375 select OF_EARLY_FLATTREE
393 tristate "Host file-based simulated block device support"
402 int "Number of host file-based simulated block devices"
425 Another simulated disk in a host file for a buildroot-independent
450 bool "Use 8-bit access to XTFPGA LCD"
454 LCD may be connected with 4- or 8-bit interface, 8-bit access may
455 only be used with 8-bit interface. Please consult prototyping user
471 This unfortunately won't work for U-Boot and likely also wont
477 xt-gdb can't place a Software Breakpoint in the 0XD region prior
485 Selecting this will cause U-Boot to set the KERNEL Load and Entry
491 bool "Kernel Execute-In-Place from ROM"
494 Execute-In-Place allows the kernel to run from non-volatile storage
497 to RAM. Read-write sections, such as the data section and stack,
518 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,
519 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.
538 2: WB, no-write-allocate cache,
584 placed at their hardware-defined locations.
601 XIP-aware MTD support.
643 MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting
652 TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000
660 TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000