272 	int i;  in op_mux_switch_ctrl()  local
275 	for (i = 0; i < num_counters; ++i) {  in op_mux_switch_ctrl()
276 		int virt = op_x86_phys_to_virt(i);  in op_mux_switch_ctrl()
279 		rdmsrl(msrs->controls[i].addr, val);  in op_mux_switch_ctrl()
282 		wrmsrl(msrs->controls[i].addr, val);  in op_mux_switch_ctrl()
292 	int i;  in op_amd_shutdown()  local
294 	for (i = 0; i < num_counters; ++i) {  in op_amd_shutdown()
295 		if (!msrs->counters[i].addr)  in op_amd_shutdown()
297 		release_perfctr_nmi(MSR_K7_PERFCTR0 + i);  in op_amd_shutdown()
298 		release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);  in op_amd_shutdown()
304 	int i;  in op_amd_fill_in_addresses()  local
306 	for (i = 0; i < num_counters; i++) {  in op_amd_fill_in_addresses()
307 		if (!reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))  in op_amd_fill_in_addresses()
309 		if (!reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) {  in op_amd_fill_in_addresses()
310 			release_perfctr_nmi(MSR_K7_PERFCTR0 + i);  in op_amd_fill_in_addresses()
315 			msrs->counters[i].addr = MSR_F15H_PERF_CTR + (i << 1);  in op_amd_fill_in_addresses()
316 			msrs->controls[i].addr = MSR_F15H_PERF_CTL + (i << 1);  in op_amd_fill_in_addresses()
318 			msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;  in op_amd_fill_in_addresses()
319 			msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;  in op_amd_fill_in_addresses()
323 		if (!counter_config[i].enabled)  in op_amd_fill_in_addresses()
325 		op_x86_warn_reserved(i);  in op_amd_fill_in_addresses()
337 	int i;  in op_amd_setup_ctrs()  local
340 	for (i = 0; i < OP_MAX_COUNTER; ++i) {  in op_amd_setup_ctrs()
341 		if (counter_config[i].enabled  in op_amd_setup_ctrs()
342 		    && msrs->counters[op_x86_virt_to_phys(i)].addr)  in op_amd_setup_ctrs()
343 			reset_value[i] = counter_config[i].count;  in op_amd_setup_ctrs()
345 			reset_value[i] = 0;  in op_amd_setup_ctrs()
349 	for (i = 0; i < num_counters; ++i) {  in op_amd_setup_ctrs()
350 		if (!msrs->controls[i].addr)  in op_amd_setup_ctrs()
352 		rdmsrl(msrs->controls[i].addr, val);  in op_amd_setup_ctrs()
354 			op_x86_warn_in_use(i);  in op_amd_setup_ctrs()
356 		wrmsrl(msrs->controls[i].addr, val);  in op_amd_setup_ctrs()
361 		wrmsrl(msrs->counters[i].addr, -1LL);  in op_amd_setup_ctrs()
365 	for (i = 0; i < num_counters; ++i) {  in op_amd_setup_ctrs()
366 		int virt = op_x86_phys_to_virt(i);  in op_amd_setup_ctrs()
371 		wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);  in op_amd_setup_ctrs()
374 		rdmsrl(msrs->controls[i].addr, val);  in op_amd_setup_ctrs()
377 		wrmsrl(msrs->controls[i].addr, val);  in op_amd_setup_ctrs()
385 	int i;  in op_amd_check_ctrs()  local
387 	for (i = 0; i < num_counters; ++i) {  in op_amd_check_ctrs()
388 		int virt = op_x86_phys_to_virt(i);  in op_amd_check_ctrs()
391 		rdmsrl(msrs->counters[i].addr, val);  in op_amd_check_ctrs()
396 		wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);  in op_amd_check_ctrs()
408 	int i;  in op_amd_start()  local
410 	for (i = 0; i < num_counters; ++i) {  in op_amd_start()
411 		if (!reset_value[op_x86_phys_to_virt(i)])  in op_amd_start()
413 		rdmsrl(msrs->controls[i].addr, val);  in op_amd_start()
415 		wrmsrl(msrs->controls[i].addr, val);  in op_amd_start()
424 	int i;  in op_amd_stop()  local
430 	for (i = 0; i < num_counters; ++i) {  in op_amd_stop()
431 		if (!reset_value[op_x86_phys_to_virt(i)])  in op_amd_stop()
433 		rdmsrl(msrs->controls[i].addr, val);  in op_amd_stop()
435 		wrmsrl(msrs->controls[i].addr, val);  in op_amd_stop()