172 static inline struct kvm_pmc *get_fw_gp_pmc(struct kvm_pmu *pmu, u32 msr)  in get_fw_gp_pmc()  argument
177 	return get_gp_pmc(pmu, msr, MSR_IA32_PMC0);  in get_fw_gp_pmc()
180 static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)  in intel_is_valid_msr()  argument
185 	switch (msr) {  in intel_is_valid_msr()
193 		ret = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0) ||  in intel_is_valid_msr()
194 			get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0) ||  in intel_is_valid_msr()
195 			get_fixed_pmc(pmu, msr) || get_fw_gp_pmc(pmu, msr);  in intel_is_valid_msr()
202 static struct kvm_pmc *intel_msr_idx_to_pmc(struct kvm_vcpu *vcpu, u32 msr)  in intel_msr_idx_to_pmc()  argument
207 	pmc = get_fixed_pmc(pmu, msr);  in intel_msr_idx_to_pmc()
208 	pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0);  in intel_msr_idx_to_pmc()
209 	pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0);  in intel_msr_idx_to_pmc()
218 	u32 msr = msr_info->index;  in intel_pmu_get_msr()  local
220 	switch (msr) {  in intel_pmu_get_msr()
234 		if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||  in intel_pmu_get_msr()
235 		    (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) {  in intel_pmu_get_msr()
240 		} else if ((pmc = get_fixed_pmc(pmu, msr))) {  in intel_pmu_get_msr()
245 		} else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {  in intel_pmu_get_msr()
258 	u32 msr = msr_info->index;  in intel_pmu_set_msr()  local
261 	switch (msr) {  in intel_pmu_set_msr()
293 		if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||  in intel_pmu_set_msr()
294 		    (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) {  in intel_pmu_set_msr()
295 			if ((msr & MSR_PMC_FULL_WIDTH_BIT) &&  in intel_pmu_set_msr()
299 			    !(msr & MSR_PMC_FULL_WIDTH_BIT))  in intel_pmu_set_msr()
306 		} else if ((pmc = get_fixed_pmc(pmu, msr))) {  in intel_pmu_set_msr()
312 		} else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {  in intel_pmu_set_msr()