1 // SPDX-License-Identifier: GPL-2.0
8  * print a warning if not and turn off the TSC clock-source.
10  * The warp-check is point-to-point between two CPUs, the CPU
14  * Only two CPUs may participate - they can enter in any order.
36  * TSC's on different sockets may be reset asynchronously.
37  * This may cause the TSC ADJUST value on socket 0 to be NOT 0.
62 	if (!resume && time_before(jiffies, adj->nextcheck))  in tsc_verify_tsc_adjust()
65 	adj->nextcheck = jiffies + HZ;  in tsc_verify_tsc_adjust()
68 	if (adj->adjusted == curval)  in tsc_verify_tsc_adjust()
72 	wrmsrl(MSR_IA32_TSC_ADJUST, adj->adjusted);  in tsc_verify_tsc_adjust()
74 	if (!adj->warned || resume) {  in tsc_verify_tsc_adjust()
75 		pr_warn(FW_BUG "TSC ADJUST differs: CPU%u %lld --> %lld. Restoring\n",  in tsc_verify_tsc_adjust()
76 			smp_processor_id(), adj->adjusted, curval);  in tsc_verify_tsc_adjust()
77 		adj->warned = true;  in tsc_verify_tsc_adjust()
88  * is always on.
130 	 * On the boot cpu we just force set the ADJUST value to 0 if it's  in tsc_sanitize_first_cpu()
131 	 * non zero. We don't do that on non boot cpus because physical  in tsc_sanitize_first_cpu()
151 	cur->adjusted = bootval;  in tsc_sanitize_first_cpu()
168 	cur->bootval = bootval;  in tsc_store_and_check_tsc_adjust()
169 	cur->nextcheck = jiffies + HZ;  in tsc_store_and_check_tsc_adjust()
190 	cur->bootval = bootval;  in tsc_store_and_check_tsc_adjust()
191 	cur->nextcheck = jiffies + HZ;  in tsc_store_and_check_tsc_adjust()
192 	cur->warned = false;  in tsc_store_and_check_tsc_adjust()
195 	 * If a non-zero TSC value for socket 0 may be valid then the default  in tsc_store_and_check_tsc_adjust()
199 		cur->adjusted = bootval;  in tsc_store_and_check_tsc_adjust()
205 	 * where TSC_ADJUST is expected to be different. When called on the  in tsc_store_and_check_tsc_adjust()
222 	if (bootval != ref->bootval)  in tsc_store_and_check_tsc_adjust()
227 	 * value on this newly upcoming CPU differs from the adjustment  in tsc_store_and_check_tsc_adjust()
231 	if (bootval != ref->adjusted) {  in tsc_store_and_check_tsc_adjust()
232 		cur->adjusted = ref->adjusted;  in tsc_store_and_check_tsc_adjust()
233 		wrmsrl(MSR_IA32_TSC_ADJUST, ref->adjusted);  in tsc_store_and_check_tsc_adjust()
236 	 * We have the TSCs forced to be in sync on this package. Skip sync  in tsc_store_and_check_tsc_adjust()
253  * we want to have the fastest, inlined, non-debug version
254  * of a critical section, to be able to prove TSC time-warps:
264  * TSC-warp measurement loop running on both CPUs.  This is not called
274 	 * The measurement runs for 'timeout' msecs:  in check_tsc_warp()
281 		 * previous TSC that was measured (possibly on  in check_tsc_warp()
304 		 * we saw a time-warp of the TSC going backwards:  in check_tsc_warp()
308 			max_warp = max(max_warp, prev - now);  in check_tsc_warp()
321 	WARN(!(now-start),  in check_tsc_warp()
323 			now-start, end-start);  in check_tsc_warp()
328  * If the target CPU coming online doesn't have any of its core-siblings
329  * online, a timeout of 20msec will be used for the TSC-warp measurement
332  * have more and more logical-siblings in that socket).
334  * Ideally we should be able to skip the TSC sync check on the other
335  * core-siblings, if the first logical CPU in a socket passed the sync test.
336  * But as the TSC is per-logical CPU and can potentially be modified wrongly
347  * Source CPU calls into this - it waits for the freshly booted
362 	 * Set the maximum number of test runs to  in check_tsc_sync_source()
374 	while (atomic_read(&start_count) != cpus - 1) {  in check_tsc_sync_source()
389 	while (atomic_read(&stop_count) != cpus-1)  in check_tsc_sync_source()
393 	 * If the test was successful set the number of runs to zero and  in check_tsc_sync_source()
394 	 * stop. If not, decrement the number of runs an check if we can  in check_tsc_sync_source()
400 		pr_debug("TSC synchronization [CPU#%d -> CPU#%d]: passed\n",  in check_tsc_sync_source()
407 		pr_warn("TSC synchronization [CPU#%d -> CPU#%d]:\n",  in check_tsc_sync_source()
417 	 * Reset it - just in case we boot another CPU later:  in check_tsc_sync_source()
456 	 * is true for SoCs which have no fallback clocksource. On these  in check_tsc_sync_target()
498 	 * Check the number of remaining test runs. If not zero, the test  in check_tsc_sync_target()
511 		cur_max_warp = -gbl_max_warp;  in check_tsc_sync_target()
518 	 * really depends on CPU, node distance and frequency. So  in check_tsc_sync_target()
524 	cur->adjusted += cur_max_warp;  in check_tsc_sync_target()
527 		cpu, cur_max_warp, cur->adjusted);  in check_tsc_sync_target()
529 	wrmsrl(MSR_IA32_TSC_ADJUST, cur->adjusted);  in check_tsc_sync_target()