Lines Matching +full:0 +full:x8000000a

14 	INTERCEPT_CR = 0,
24 	/* Byte offset 000h (word 0) */
25 	INTERCEPT_CR0_READ = 0,
143 	u64 avic_backing_page;	/* Offset 0xe0 */
144 	u8 reserved_6[8];	/* Offset 0xe8 */
145 	u64 avic_logical_id;	/* Offset 0xf0 */
146 	u64 avic_physical_id;	/* Offset 0xf8 */
150 #define TLB_CONTROL_DO_NOTHING 0
155 #define V_TPR_MASK 0x0f
164 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
180 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
196 #define SVM_VM_CR_VALID_MASK	0x001fULL
197 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
198 #define SVM_VM_CR_SVM_DIS_MASK  0x0010ULL
200 #define SVM_NESTED_CTL_NP_ENABLE	BIT(0)
259 	u64 reserved_8;		/* rax already available at 0x01f8 */
263 	u64 reserved_9;		/* rsp already available at 0x01d8 */
315 #define SVM_CPUID_FUNC 0x8000000a
327 #define SVM_SELECTOR_TYPE_MASK (0xf)
340 #define SVM_EVTINJ_VEC_MASK 0xff
345 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
368 #define SVM_EXITINFO_REG_MASK 0x0F