include/asm/cpufeatures.h

1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/required-features.h>
10 #include <asm/disabled-features.h>
14  * Defines x86 CPU feature bits
16 #define NCAPINTS			19	   /* N 32-bit words worth of info */
17 #define NBUGINTS			1	   /* N 32-bit bug flags */
25  * please update the table in kernel/cpu/cpuid-deps.c as well.
28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
34 #define X86_FEATURE_MSR			( 0*32+ 5) /* Model-Specific Registers */
37 #define X86_FEATURE_CX8			( 0*32+ 8) /* CMPXCHG8 instruction */
45 #define X86_FEATURE_PSE36		( 0*32+17) /* 36-bit PSEs */
54 #define X86_FEATURE_SELFSNOOP		( 0*32+27) /* "ss" CPU self snoop */
55 #define X86_FEATURE_HT			( 0*32+28) /* Hyper-Threading */
57 #define X86_FEATURE_IA64		( 0*32+30) /* IA-64 processor */
60 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
69 #define X86_FEATURE_LM			( 1*32+29) /* Long Mode (x86-64, 64-bit support) */
73 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
74 #define X86_FEATURE_RECOVERY		( 2*32+ 0) /* CPU in recovery mode */
78 /* Other features, Linux-defined mapping, word 3 */
85 /* CPU types for specific tunings: */
90 #define X86_FEATURE_CONSTANT_TSC	( 3*32+ 8) /* TSC ticks at a constant rate */
94 #define X86_FEATURE_PEBS		( 3*32+12) /* Precise-Event Based Sampling */
99 #define X86_FEATURE_SME_COHERENT	( 3*32+17) /* "" AMD hardware-enforced cache coherency */
103 #define X86_FEATURE_ALWAYS		( 3*32+21) /* "" Always-present feature */
104 #define X86_FEATURE_XTOPOLOGY		( 3*32+22) /* CPU topology enum extensions */
107 #define X86_FEATURE_CPUID		( 3*32+25) /* CPU has CPUID instruction itself */
108 #define X86_FEATURE_EXTD_APICID		( 3*32+26) /* Extended APICID (8 bits) */
109 #define X86_FEATURE_AMD_DCM		( 3*32+27) /* AMD multi-node processor */
110 #define X86_FEATURE_APERFMPERF		( 3*32+28) /* P-State hardware coordination feedback capability (AP…
115 /* Intel-defined CPU features, CPUID level 0x00000001 (ECX), word 4 */
116 #define X86_FEATURE_XMM3		( 4*32+ 0) /* "pni" SSE-3 */
118 #define X86_FEATURE_DTES64		( 4*32+ 2) /* 64-bit Debug Store */
120 #define X86_FEATURE_DSCPL		( 4*32+ 4) /* "ds_cpl" CPL-qualified (filtered) Debug Store */
124 #define X86_FEATURE_TM2			( 4*32+ 8) /* Thermal Monitor 2 */
125 #define X86_FEATURE_SSSE3		( 4*32+ 9) /* Supplemental SSE-3 */
128 #define X86_FEATURE_FMA			( 4*32+12) /* Fused multiply-add */
134 #define X86_FEATURE_XMM4_1		( 4*32+19) /* "sse4_1" SSE-4.1 */
135 #define X86_FEATURE_XMM4_2		( 4*32+20) /* "sse4_2" SSE-4.2 */
144 #define X86_FEATURE_F16C		( 4*32+29) /* 16-bit FP conversions */
148 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
151 #define X86_FEATURE_XCRYPT		( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
152 #define X86_FEATURE_XCRYPT_EN		( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
153 #define X86_FEATURE_ACE2		( 5*32+ 8) /* Advanced Cryptography Engine v2 */
165 #define X86_FEATURE_CR8_LEGACY		( 6*32+ 4) /* CR8 in 32-bit mode */
167 #define X86_FEATURE_SSE4A		( 6*32+ 6) /* SSE-4A */
169 #define X86_FEATURE_3DNOWPREFETCH	( 6*32+ 8) /* 3DNow prefetch instructions */
184 #define X86_FEATURE_PTSC		( 6*32+27) /* Performance time-stamp counter */
189  * Auxiliary flags: Linux defined - For features scattered in various
202 #define X86_FEATURE_HW_PSTATE		( 7*32+ 8) /* AMD HW-PState */
207 #define X86_FEATURE_RSB_VMEXIT		( 7*32+13) /* "" Fill RSB on VM-Exit */
222 #define X86_FEATURE_ZEN			( 7*32+28) /* "" CPU is AMD family 0x17 or above (Zen) */
227 /* Virtualization flags: Linux defined, word 8 */
228 #define X86_FEATURE_TPR_SHADOW		( 8*32+ 0) /* Intel TPR Shadow */
229 #define X86_FEATURE_VNMI		( 8*32+ 1) /* Intel Virtual NMI */
230 #define X86_FEATURE_FLEXPRIORITY	( 8*32+ 2) /* Intel FlexPriority */
231 #define X86_FEATURE_EPT			( 8*32+ 3) /* Intel Extended Page Table */
232 #define X86_FEATURE_VPID		( 8*32+ 4) /* Intel Virtual Processor ID */
234 #define X86_FEATURE_VMMCALL		( 8*32+15) /* Prefer VMMCALL to VMCALL */
235 #define X86_FEATURE_XENPV		( 8*32+16) /* "" Xen paravirtual guest */
236 #define X86_FEATURE_EPT_AD		( 8*32+17) /* Intel Extended Page Table access-dirty bit */
237 #define X86_FEATURE_VMCALL		( 8*32+18) /* "" Hypervisor supports the VMCALL instruction */
238 #define X86_FEATURE_VMW_VMMCALL		( 8*32+19) /* "" VMware prefers VMMCALL hypercall instruction */
239 #define X86_FEATURE_SEV_ES		( 8*32+20) /* AMD Secure Encrypted Virtualization - Encrypted State */
241 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
249 #define X86_FEATURE_BMI2		( 9*32+ 8) /* 2nd group bit manipulation extensions */
257 #define X86_FEATURE_AVX512F		( 9*32+16) /* AVX-512 Foundation */
258 #define X86_FEATURE_AVX512DQ		( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */
262 #define X86_FEATURE_AVX512IFMA		( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */
266 #define X86_FEATURE_AVX512PF		( 9*32+26) /* AVX-512 Prefetch */
267 #define X86_FEATURE_AVX512ER		( 9*32+27) /* AVX-512 Exponential and Reciprocal */
268 #define X86_FEATURE_AVX512CD		( 9*32+28) /* AVX-512 Conflict Detection */
270 #define X86_FEATURE_AVX512BW		( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */
271 #define X86_FEATURE_AVX512VL		( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */
280  * Extended auxiliary flags: Linux defined - for features scattered in various
292 #define X86_FEATURE_PER_THREAD_MBA	(11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
293 /* FREE!				(11*32+ 8) */
305 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
308 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
317 …MD_STIBP_ALWAYS_ON	(13*32+17) /* "" Single Thread Indirect Branch Predictors always-on preferred */
330 #define X86_FEATURE_HWP			(14*32+ 7) /* Intel Hardware P-states */
331 #define X86_FEATURE_HWP_NOTIFY		(14*32+ 8) /* HWP Notification */
343 #define X86_FEATURE_FLUSHBYASID		(15*32+ 6) /* flush-by-ASID support */
351 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
358 #define X86_FEATURE_GFNI		(16*32+ 8) /* Galois Field New Instructions */
360 #define X86_FEATURE_VPCLMULQDQ		(16*32+10) /* Carry-Less Multiplication Double Quadword */
362 #define X86_FEATURE_AVX512_BITALG	(16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB instruct…
365 #define X86_FEATURE_LA57		(16*32+16) /* 5-level page tables */
372 /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
377 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
378 #define X86_FEATURE_AVX512_4VNNIW	(18*32+ 2) /* AVX-512 Neural Network Instructions */
379 #define X86_FEATURE_AVX512_4FMAPS	(18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
381 #define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* AVX-512 Intersect for D/Q */
383 #define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU buffers */
409 #define X86_BUG_SYSRET_SS_ATTRS		X86_BUG(8) /* SYSRET doesn't fix up SS attrs */
412  * 64-bit kernels don't use X86_BUG_ESPFIX.  Make the define conditional
415 #define X86_BUG_ESPFIX			X86_BUG(9) /* "" IRET to 16-bit SS corrupts ESP/RSP high bits */
419 #define X86_BUG_MONITOR			X86_BUG(12) /* IPI required to wake up remote CPU */
420 #define X86_BUG_AMD_E400		X86_BUG(13) /* CPU is among the affected by Erratum 400 */
421 #define X86_BUG_CPU_MELTDOWN		X86_BUG(14) /* CPU is affected by meltdown attack and needs kernel pa…
422 #define X86_BUG_SPECTRE_V1		X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditi…
423 #define X86_BUG_SPECTRE_V2		X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirec…
424 #define X86_BUG_SPEC_STORE_BYPASS	X86_BUG(17) /* CPU is affected by speculative store bypass attack…
425 #define X86_BUG_L1TF			X86_BUG(18) /* CPU is affected by L1 Terminal Fault */
426 #define X86_BUG_MDS			X86_BUG(19) /* CPU is affected by Microarchitectural data sampling */
427 #define X86_BUG_MSBDS_ONLY		X86_BUG(20) /* CPU is only affected by the  MSDBS variant of BUG_MDS */
428 #define X86_BUG_SWAPGS			X86_BUG(21) /* CPU is affected by speculation through SWAPGS */
429 #define X86_BUG_TAA			X86_BUG(22) /* CPU is affected by TSX Async Abort(TAA) */
430 #define X86_BUG_ITLB_MULTIHIT		X86_BUG(23) /* CPU may incur MCE during certain page attribute chang…
431 #define X86_BUG_SRBDS			X86_BUG(24) /* CPU may leak RNG bits if not mitigated */
432 #define X86_BUG_MMIO_STALE_DATA		X86_BUG(25) /* CPU is affected by Processor MMIO Stale Data vulner…
433 #define X86_BUG_MMIO_UNKNOWN		X86_BUG(26) /* CPU is too old and its MMIO Stale Data status is unkno…
434 #define X86_BUG_RETBLEED		X86_BUG(27) /* CPU is affected by RETBleed */