1087 	if (!(cpuc->pebs_enabled & ~PEBS_VIA_PT_MASK))  in intel_pmu_pebs_via_pt_disable()
1088 		cpuc->pebs_enabled &= ~PEBS_VIA_PT_MASK;  in intel_pmu_pebs_via_pt_disable()
1101 		cpuc->pebs_enabled |= PEBS_PMI_AFTER_EACH_RECORD;  in intel_pmu_pebs_via_pt_enable()
1103 	cpuc->pebs_enabled |= PEBS_OUTPUT_PT;  in intel_pmu_pebs_via_pt_enable()
1116 	cpuc->pebs_enabled |= 1ULL << hwc->idx;  in intel_pmu_pebs_enable()
1119 		cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);  in intel_pmu_pebs_enable()
1121 		cpuc->pebs_enabled |= 1ULL << 63;  in intel_pmu_pebs_enable()
1173 	cpuc->pebs_enabled &= ~(1ULL << hwc->idx);  in intel_pmu_pebs_disable()
1177 		cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));  in intel_pmu_pebs_disable()
1179 		cpuc->pebs_enabled &= ~(1ULL << 63);  in intel_pmu_pebs_disable()
1184 		wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);  in intel_pmu_pebs_disable()
1193 	if (cpuc->pebs_enabled)  in intel_pmu_pebs_enable_all()
1194 		wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);  in intel_pmu_pebs_enable_all()
1201 	if (cpuc->pebs_enabled)  in intel_pmu_pebs_disable_all()
1650 			pebs_status = status & cpuc->pebs_enabled;  in get_next_pebs_record_by_bit()
1839 	for_each_set_bit(bit, (unsigned long *)&cpuc->pebs_enabled, size) {  in intel_pmu_pebs_event_update_no_drain()
1881 		pebs_status = p->status & cpuc->pebs_enabled;  in intel_pmu_drain_pebs_nhm()
1900 		if (!pebs_status && cpuc->pebs_enabled &&  in intel_pmu_drain_pebs_nhm()
1901 			!(cpuc->pebs_enabled & (cpuc->pebs_enabled-1)))  in intel_pmu_drain_pebs_nhm()
1902 			pebs_status = p->status = cpuc->pebs_enabled;  in intel_pmu_drain_pebs_nhm()
1990 		pebs_status = get_pebs_status(at) & cpuc->pebs_enabled;  in intel_pmu_drain_pebs_icl()