events/intel/ds.c

56 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
69 	OP_LH | P(LVL, L3)  | LEVEL(L3) | P(SNOOP, HIT),   /* 0x06: L3 hit, snoop hit */
71 	OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT),  /* 0x08: L3 miss snoop hit */
73 	OP_LH | P(LVL, LOC_RAM)  | LEVEL(RAM) | P(SNOOP, HIT),       /* 0x0a: L3 miss, shared */
74 	OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT),  /* 0x0b: L3 miss, shared */
84 	pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);  in intel_pmu_pebs_data_source_nhm()
93 	pebs_data_source[0x08] = OP_LH | pmem_or_l4 | P(SNOOP, HIT);  in intel_pmu_pebs_data_source_skl()
94 	pebs_data_source[0x09] = OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT);  in intel_pmu_pebs_data_source_skl()
117 		val |= P(TLB, HIT);  in precise_store_data()
125 		val |= P(LVL, HIT);  in precise_store_data()
193 		val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);  in load_latency_data()