21 static u32 ibs_caps;  variable
356 		if (ibs_caps & IBS_CAPS_OPCNTEXT)  in get_ibs_op_count()
358 	} else if (ibs_caps & IBS_CAPS_RDWROPCNT) {  in get_ibs_op_count()
430 	if (perf_ibs == &perf_ibs_op && (ibs_caps & IBS_CAPS_OPCNTEXT)) {  in perf_ibs_start()
643 	ibs_data.caps = ibs_caps;  in perf_ibs_handle_irq()
646 	check_rip = (perf_ibs == &perf_ibs_op && (ibs_caps & IBS_CAPS_RIPINVALIDCHK));  in perf_ibs_handle_irq()
667 			if (ibs_caps & IBS_CAPS_BRNTRGT) {  in perf_ibs_handle_irq()
671 			if (ibs_caps & IBS_CAPS_OPDATA4) {  in perf_ibs_handle_irq()
676 		if (perf_ibs == &perf_ibs_fetch && (ibs_caps & IBS_CAPS_FETCHCTLEXTD)) {  in perf_ibs_handle_irq()
719 			if (ibs_caps & IBS_CAPS_OPCNTEXT) {  in perf_ibs_handle_irq()
723 			if ((ibs_caps & IBS_CAPS_RDWROPCNT) && (*config & IBS_OP_CNT_CTL))  in perf_ibs_handle_irq()
804 	if (ibs_caps & IBS_CAPS_OPCNT) {  in perf_event_ibs_init()
809 	if (ibs_caps & IBS_CAPS_OPCNTEXT) {  in perf_event_ibs_init()
823 	pr_info("perf: AMD IBS detected (0x%08x)\n", ibs_caps);  in perf_event_ibs_init()
872 	return ibs_caps;  in get_ibs_caps()
1101 	ibs_caps = caps;  in amd_ibs_init()