Lines Matching refs:hose
66 static int fsl_pcie_check_link(struct pci_controller *hose) in fsl_pcie_check_link() argument
70 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) { in fsl_pcie_check_link()
71 if (hose->ops->read == fsl_indirect_read_config) in fsl_pcie_check_link()
72 __indirect_read_config(hose, hose->first_busno, 0, in fsl_pcie_check_link()
75 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); in fsl_pcie_check_link()
79 struct ccsr_pci __iomem *pci = hose->private_data; in fsl_pcie_check_link()
93 struct pci_controller *hose = pci_bus_to_host(bus); in fsl_indirect_read_config() local
95 if (fsl_pcie_check_link(hose)) in fsl_indirect_read_config()
96 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; in fsl_indirect_read_config()
98 hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK; in fsl_indirect_read_config()
116 struct pci_controller *hose = pci_bus_to_host(pdev->bus); in pci_dma_dev_setup_swiotlb() local
119 hose->dma_window_base_cur + hose->dma_window_size - 1; in pci_dma_dev_setup_swiotlb()
122 static void setup_swiotlb_ops(struct pci_controller *hose) in setup_swiotlb_ops() argument
125 hose->controller_ops.dma_dev_setup = pci_dma_dev_setup_swiotlb; in setup_swiotlb_ops()
128 static inline void setup_swiotlb_ops(struct pci_controller *hose) {} in setup_swiotlb_ops() argument
193 static void setup_pci_atmu(struct pci_controller *hose) in setup_pci_atmu() argument
195 struct ccsr_pci __iomem *pci = hose->private_data; in setup_pci_atmu()
215 if (of_device_is_compatible(hose->dn, "fsl,bsc9132-pcie")) { in setup_pci_atmu()
228 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { in setup_pci_atmu()
247 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM)) in setup_pci_atmu()
250 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start); in setup_pci_atmu()
251 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end); in setup_pci_atmu()
254 offset = hose->mem_offset[i]; in setup_pci_atmu()
255 n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset); in setup_pci_atmu()
259 hose->mem_resources[i].flags |= IORESOURCE_DISABLED; in setup_pci_atmu()
265 if (hose->io_resource.flags & IORESOURCE_IO) { in setup_pci_atmu()
271 (u64)hose->io_resource.start, in setup_pci_atmu()
272 (u64)resource_size(&hose->io_resource), in setup_pci_atmu()
273 (u64)hose->io_base_phys); in setup_pci_atmu()
274 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12)); in setup_pci_atmu()
276 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12)); in setup_pci_atmu()
279 | (ilog2(hose->io_resource.end in setup_pci_atmu()
280 - hose->io_resource.start + 1) - 1)); in setup_pci_atmu()
289 pr_err("%pOF: No outbound window space\n", hose->dn); in setup_pci_atmu()
294 pr_err("%pOF: No space for inbound window\n", hose->dn); in setup_pci_atmu()
299 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff); in setup_pci_atmu()
300 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); in setup_pci_atmu()
308 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar); in setup_pci_atmu()
312 pr_info("%pOF: PCICSRBAR @ 0x%x\n", hose->dn, pcicsrbar); in setup_pci_atmu()
330 reg = of_get_property(hose->dn, "msi-address-64", &len); in setup_pci_atmu()
335 pr_info("%pOF: extending DDR ATMU to cover MSIIR", hose->dn); in setup_pci_atmu()
340 "unsupported\n", hose->dn, address); in setup_pci_atmu()
348 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { in setup_pci_atmu()
354 "greater than memory size\n", hose->dn); in setup_pci_atmu()
367 hose->dma_window_base_cur = 0x00000000; in setup_pci_atmu()
368 hose->dma_window_size = (resource_size_t)sz; in setup_pci_atmu()
401 pr_info("%pOF: Setup 64-bit PCI DMA window\n", hose->dn); in setup_pci_atmu()
434 hose->dma_window_base_cur = 0x00000000; in setup_pci_atmu()
435 hose->dma_window_size = (resource_size_t)paddr; in setup_pci_atmu()
438 if (hose->dma_window_size < mem) { in setup_pci_atmu()
444 hose->dn); in setup_pci_atmu()
451 hose->dn); in setup_pci_atmu()
453 pr_info("%pOF: DMA window size is 0x%llx\n", hose->dn, in setup_pci_atmu()
454 (u64)hose->dma_window_size); in setup_pci_atmu()
458 static void __init setup_pci_cmd(struct pci_controller *hose) in setup_pci_cmd() argument
463 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); in setup_pci_cmd()
466 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); in setup_pci_cmd()
468 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX); in setup_pci_cmd()
473 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd); in setup_pci_cmd()
475 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); in setup_pci_cmd()
481 struct pci_controller *hose = pci_bus_to_host(bus); in fsl_pcibios_fixup_bus() local
493 is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP); in fsl_pcibios_fixup_bus()
494 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK); in fsl_pcibios_fixup_bus()
496 if (bus->parent == hose->bus && (is_pcie || no_link)) { in fsl_pcibios_fixup_bus()
504 par = &hose->io_resource; in fsl_pcibios_fixup_bus()
506 par = &hose->mem_resources[i-1]; in fsl_pcibios_fixup_bus()
519 struct pci_controller *hose; in fsl_add_bridge() local
551 hose = pcibios_alloc_controller(dev); in fsl_add_bridge()
552 if (!hose) in fsl_add_bridge()
556 hose->parent = &pdev->dev; in fsl_add_bridge()
557 hose->first_busno = bus_range ? bus_range[0] : 0x0; in fsl_add_bridge()
558 hose->last_busno = bus_range ? bus_range[1] : 0xff; in fsl_add_bridge()
563 pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc)); in fsl_add_bridge()
564 if (!hose->private_data) in fsl_add_bridge()
567 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, in fsl_add_bridge()
571 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; in fsl_add_bridge()
573 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { in fsl_add_bridge()
575 hose->ops = &fsl_indirect_pcie_ops; in fsl_add_bridge()
577 early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type); in fsl_add_bridge()
583 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif); in fsl_add_bridge()
589 setup_pci_cmd(hose); in fsl_add_bridge()
592 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { in fsl_add_bridge()
593 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | in fsl_add_bridge()
595 if (fsl_pcie_check_link(hose)) in fsl_add_bridge()
596 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; in fsl_add_bridge()
599 early_read_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, &class_code); in fsl_add_bridge()
602 early_write_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, class_code); in fsl_add_bridge()
618 !early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX)) { in fsl_add_bridge()
619 early_read_config_word(hose, 0, 0, in fsl_add_bridge()
622 early_write_config_word(hose, 0, 0, in fsl_add_bridge()
629 (unsigned long long)rsrc.start, hose->first_busno, in fsl_add_bridge()
630 hose->last_busno); in fsl_add_bridge()
633 hose, hose->cfg_addr, hose->cfg_data); in fsl_add_bridge()
637 pci_process_bridge_OF_ranges(hose, dev, is_primary); in fsl_add_bridge()
640 setup_pci_atmu(hose); in fsl_add_bridge()
643 setup_swiotlb_ops(hose); in fsl_add_bridge()
648 iounmap(hose->private_data); in fsl_add_bridge()
650 if (((unsigned long)hose->cfg_data & PAGE_MASK) != in fsl_add_bridge()
651 ((unsigned long)hose->cfg_addr & PAGE_MASK)) in fsl_add_bridge()
652 iounmap(hose->cfg_data); in fsl_add_bridge()
653 iounmap(hose->cfg_addr); in fsl_add_bridge()
654 pcibios_free_controller(hose); in fsl_add_bridge()
688 struct pci_controller *hose = pci_bus_to_host(bus); in mpc83xx_pcie_exclude_device() local
690 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) in mpc83xx_pcie_exclude_device()
697 if (bus->number == hose->first_busno || in mpc83xx_pcie_exclude_device()
698 bus->primary == hose->first_busno) { in mpc83xx_pcie_exclude_device()
704 if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) in mpc83xx_pcie_exclude_device()
714 struct pci_controller *hose = pci_bus_to_host(bus); in mpc83xx_pcie_remap_cfg() local
715 struct mpc83xx_pcie_priv *pcie = hose->dn->data; in mpc83xx_pcie_remap_cfg()
726 if (bus->number == hose->first_busno) in mpc83xx_pcie_remap_cfg()
742 struct pci_controller *hose = pci_bus_to_host(bus); in mpc83xx_pcie_write_config() local
745 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno) in mpc83xx_pcie_write_config()
757 static int __init mpc83xx_pcie_setup(struct pci_controller *hose, in mpc83xx_pcie_setup() argument
783 WARN_ON(hose->dn->data); in mpc83xx_pcie_setup()
784 hose->dn->data = pcie; in mpc83xx_pcie_setup()
785 hose->ops = &mpc83xx_pcie_ops; in mpc83xx_pcie_setup()
786 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; in mpc83xx_pcie_setup()
791 if (fsl_pcie_check_link(hose)) in mpc83xx_pcie_setup()
792 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; in mpc83xx_pcie_setup()
807 struct pci_controller *hose; in mpc83xx_add_bridge() local
860 hose = pcibios_alloc_controller(dev); in mpc83xx_add_bridge()
861 if (!hose) in mpc83xx_add_bridge()
864 hose->first_busno = bus_range ? bus_range[0] : 0; in mpc83xx_add_bridge()
865 hose->last_busno = bus_range ? bus_range[1] : 0xff; in mpc83xx_add_bridge()
868 ret = mpc83xx_pcie_setup(hose, &rsrc_reg); in mpc83xx_add_bridge()
872 setup_indirect_pci(hose, rsrc_cfg.start, in mpc83xx_add_bridge()
878 (unsigned long long)rsrc_reg.start, hose->first_busno, in mpc83xx_add_bridge()
879 hose->last_busno); in mpc83xx_add_bridge()
882 hose, hose->cfg_addr, hose->cfg_data); in mpc83xx_add_bridge()
886 pci_process_bridge_OF_ranges(hose, dev, primary); in mpc83xx_add_bridge()
890 pcibios_free_controller(hose); in mpc83xx_add_bridge()
895 u64 fsl_pci_immrbar_base(struct pci_controller *hose) in fsl_pci_immrbar_base() argument
899 struct mpc83xx_pcie_priv *pcie = hose->dn->data; in fsl_pci_immrbar_base()
923 pci_bus_read_config_dword(hose->bus, in fsl_pci_immrbar_base()
1041 struct pci_controller *hose; in is_in_pci_mem_space() local
1045 list_for_each_entry(hose, &hose_list, list_node) { in is_in_pci_mem_space()
1046 if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)) in is_in_pci_mem_space()
1050 res = &hose->mem_resources[i]; in is_in_pci_mem_space()
1152 struct pci_controller *hose = dev_id; in fsl_pci_pme_handle() local
1153 struct ccsr_pci __iomem *pci = hose->private_data; in fsl_pci_pme_handle()
1165 static int fsl_pci_pme_probe(struct pci_controller *hose) in fsl_pci_pme_probe() argument
1174 dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list); in fsl_pci_pme_probe()
1181 pme_irq = irq_of_parse_and_map(hose->dn, 0); in fsl_pci_pme_probe()
1188 res = devm_request_irq(hose->parent, pme_irq, in fsl_pci_pme_probe()
1191 "[PCI] PME", hose); in fsl_pci_pme_probe()
1199 pci = hose->private_data; in fsl_pci_pme_probe()
1217 static void send_pme_turnoff_message(struct pci_controller *hose) in send_pme_turnoff_message() argument
1219 struct ccsr_pci __iomem *pci = hose->private_data; in send_pme_turnoff_message()
1238 static void fsl_pci_syscore_do_suspend(struct pci_controller *hose) in fsl_pci_syscore_do_suspend() argument
1240 send_pme_turnoff_message(hose); in fsl_pci_syscore_do_suspend()
1245 struct pci_controller *hose, *tmp; in fsl_pci_syscore_suspend() local
1247 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) in fsl_pci_syscore_suspend()
1248 fsl_pci_syscore_do_suspend(hose); in fsl_pci_syscore_suspend()
1253 static void fsl_pci_syscore_do_resume(struct pci_controller *hose) in fsl_pci_syscore_do_resume() argument
1255 struct ccsr_pci __iomem *pci = hose->private_data; in fsl_pci_syscore_do_resume()
1273 setup_pci_atmu(hose); in fsl_pci_syscore_do_resume()
1278 struct pci_controller *hose, *tmp; in fsl_pci_syscore_resume() local
1280 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) in fsl_pci_syscore_resume()
1281 fsl_pci_syscore_do_resume(hose); in fsl_pci_syscore_resume()