165 	struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);  in pnv_setup_msi_irqs()  local
172 	if (WARN_ON(!phb) || !phb->msi_bmp.bitmap)  in pnv_setup_msi_irqs()
175 	if (pdev->no_64bit_msi && !phb->msi32_support)  in pnv_setup_msi_irqs()
179 		if (!entry->msi_attrib.is_64 && !phb->msi32_support) {  in pnv_setup_msi_irqs()
184 		hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1);  in pnv_setup_msi_irqs()
190 		virq = irq_create_mapping(NULL, phb->msi_base + hwirq);  in pnv_setup_msi_irqs()
194 			msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);  in pnv_setup_msi_irqs()
197 		rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq,  in pnv_setup_msi_irqs()
202 			msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);  in pnv_setup_msi_irqs()
213 	struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);  in pnv_teardown_msi_irqs()  local
217 	if (WARN_ON(!phb))  in pnv_teardown_msi_irqs()
226 		msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, 1);  in pnv_teardown_msi_irqs()
556 static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)  in pnv_pci_handle_eeh_config()  argument
561 	spin_lock_irqsave(&phb->lock, flags);  in pnv_pci_handle_eeh_config()
564 	rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data,  in pnv_pci_handle_eeh_config()
565 					 phb->diag_data_size);  in pnv_pci_handle_eeh_config()
569 	if (phb->unfreeze_pe) {  in pnv_pci_handle_eeh_config()
570 		ret = phb->unfreeze_pe(phb,  in pnv_pci_handle_eeh_config()
574 		rc = opal_pci_eeh_freeze_clear(phb->opal_id,  in pnv_pci_handle_eeh_config()
580 				__func__, rc, phb->hose->global_number,  in pnv_pci_handle_eeh_config()
593 		pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data);  in pnv_pci_handle_eeh_config()
595 	spin_unlock_irqrestore(&phb->lock, flags);  in pnv_pci_handle_eeh_config()
600 	struct pnv_phb *phb = pdn->phb->private_data;  in pnv_pci_config_check_eeh()  local
613 		pe_no = phb->ioda.reserved_pe_idx;  in pnv_pci_config_check_eeh()
620 	if (phb->get_pe_state) {  in pnv_pci_config_check_eeh()
621 		fstate = phb->get_pe_state(phb, pe_no);  in pnv_pci_config_check_eeh()
623 		rc = opal_pci_eeh_freeze_status(phb->opal_id,  in pnv_pci_config_check_eeh()
630 				__func__, rc, phb->hose->global_number, pe_no);  in pnv_pci_config_check_eeh()
646 		if (phb->freeze_pe)  in pnv_pci_config_check_eeh()
647 			phb->freeze_pe(phb, pe_no);  in pnv_pci_config_check_eeh()
649 		pnv_pci_handle_eeh_config(phb, pe_no);  in pnv_pci_config_check_eeh()
656 	struct pnv_phb *phb = pdn->phb->private_data;  in pnv_pci_cfg_read()  local
663 		rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8);  in pnv_pci_cfg_read()
669 		rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where,  in pnv_pci_cfg_read()
676 		rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32);  in pnv_pci_cfg_read()
692 	struct pnv_phb *phb = pdn->phb->private_data;  in pnv_pci_cfg_write()  local
699 		opal_pci_config_write_byte(phb->opal_id, bdfn, where, val);  in pnv_pci_cfg_write()
702 		opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val);  in pnv_pci_cfg_write()
705 		opal_pci_config_write_word(phb->opal_id, bdfn, where, val);  in pnv_pci_cfg_write()
718 	struct pnv_phb *phb = pdn->phb->private_data;  in pnv_pci_cfg_check()  local
721 	if (!(phb->flags & PNV_PHB_FLAG_EEH))  in pnv_pci_cfg_check()
749 	struct pnv_phb *phb;  in pnv_pci_read_config()  local
761 	phb = pdn->phb->private_data;  in pnv_pci_read_config()
762 	if (phb->flags & PNV_PHB_FLAG_EEH && pdn->edev) {  in pnv_pci_read_config()
778 	struct pnv_phb *phb;  in pnv_pci_write_config()  local
789 	phb = pdn->phb->private_data;  in pnv_pci_write_config()
790 	if (!(phb->flags & PNV_PHB_FLAG_EEH))  in pnv_pci_write_config()
825 	struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus);  in pnv_pci_set_tunnel_bar()  local
836 	rc = opal_pci_get_pbcq_tunnel_bar(phb->opal_id, &val);  in pnv_pci_set_tunnel_bar()
865 	rc = opal_pci_set_pbcq_tunnel_bar(phb->opal_id, addr);  in pnv_pci_set_tunnel_bar()