61 #define IS_LE	1  macro
64 #define IS_LE	0  macro
665 		err = read_mem(&regs->gpr[reg + IS_LE], ea, 8, regs);  in emulate_lq()
691 	err = write_mem(vals[IS_LE], ea, 8, regs);  in emulate_stq()
717 		if (IS_LE && (op->vsx_flags & VSX_LDLEFT))  in emulate_vsx_load()
725 		i = IS_LE ? 8 : 8 - read_size;  in emulate_vsx_load()
732 				reg->d[IS_LE] = (signed int) reg->d[IS_LE];  in emulate_vsx_load()
735 				conv_sp_to_dp(&reg->fp[1 + IS_LE],  in emulate_vsx_load()
736 					      &reg->dp[IS_LE]);  in emulate_vsx_load()
744 				reg->d[IS_BE] = reg->d[IS_LE];  in emulate_vsx_load()
751 			i = IS_LE ? 3 - j : j;  in emulate_vsx_load()
755 			u32 val = reg->w[IS_LE ? 3 : 0];  in emulate_vsx_load()
757 				i = IS_LE ? 3 - j : j;  in emulate_vsx_load()
766 			i = IS_LE ? 7 - j : j;  in emulate_vsx_load()
774 			i = IS_LE ? 15 - j : j;  in emulate_vsx_load()
800 		if (IS_LE && (op->vsx_flags & VSX_LDLEFT))  in emulate_vsx_store()
813 		i = IS_LE ? 8 : 8 - write_size;  in emulate_vsx_store()
817 			conv_dp_to_sp(&reg->dp[IS_LE], &buf.fp[1 + IS_LE]);  in emulate_vsx_store()
834 			i = IS_LE ? 3 - j : j;  in emulate_vsx_store()
842 			i = IS_LE ? 7 - j : j;  in emulate_vsx_store()
850 			i = IS_LE ? 15 - j : j;  in emulate_vsx_store()