include/asm/opal.h

31 int64_t opal_npu_destroy_context(uint64_t phb_id, uint64_t pid, uint64_t bdf);
32 int64_t opal_npu_init_context(uint64_t phb_id, int pasid, uint64_t msr,
34 int64_t opal_npu_map_lpar(uint64_t phb_id, uint64_t bdf, uint64_t lparid,
36 int64_t opal_npu_spa_setup(uint64_t phb_id, uint32_t bdfn,
38 int64_t opal_npu_spa_clear_cache(uint64_t phb_id, uint32_t bdfn,
40 int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t bdfn, long cap,
66 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
68 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
70 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
72 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
74 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
76 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
78 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
85 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
89 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
91 int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number,
93 int64_t opal_pci_err_inject(uint64_t phb_id, uint32_t pe_no, uint32_t type,
95 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
99 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
101 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
106 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
109 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
113 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
116 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
118 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
119 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
121 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
123 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
125 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
126 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
128 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
130 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
133 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
139 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
142 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
149 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
151 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
153 int64_t opal_pci_fence_phb(uint64_t phb_id);
154 int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
155 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mas…
156 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_a…
160 int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
208 int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number);
209 int64_t opal_pci_get_pbcq_tunnel_bar(uint64_t phb_id, uint64_t *addr);
210 int64_t opal_pci_set_pbcq_tunnel_bar(uint64_t phb_id, uint64_t addr);
240 int64_t opal_pci_tce_kill(uint64_t phb_id, uint32_t kill_type,