Lines Matching refs:sli_ctl_portx
1158 union cvmx_sli_ctl_portx sli_ctl_portx; in __cvmx_pcie_rc_initialize_gen2() local
1398 sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port)); in __cvmx_pcie_rc_initialize_gen2()
1399 sli_ctl_portx.s.ptlp_ro = 1; in __cvmx_pcie_rc_initialize_gen2()
1400 sli_ctl_portx.s.ctlp_ro = 1; in __cvmx_pcie_rc_initialize_gen2()
1401 sli_ctl_portx.s.wait_com = 0; in __cvmx_pcie_rc_initialize_gen2()
1402 sli_ctl_portx.s.waitl_com = 0; in __cvmx_pcie_rc_initialize_gen2()
1403 cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port), sli_ctl_portx.u64); in __cvmx_pcie_rc_initialize_gen2()
1865 union cvmx_sli_ctl_portx sli_ctl_portx; in octeon_pcie_setup() local
2068 sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(port)); in octeon_pcie_setup()
2069 sli_ctl_portx.s.inta_map = 1; in octeon_pcie_setup()
2070 sli_ctl_portx.s.intb_map = 1; in octeon_pcie_setup()
2071 sli_ctl_portx.s.intc_map = 1; in octeon_pcie_setup()
2072 sli_ctl_portx.s.intd_map = 1; in octeon_pcie_setup()
2073 cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(port), sli_ctl_portx.u64); in octeon_pcie_setup()
2075 sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(!port)); in octeon_pcie_setup()
2076 sli_ctl_portx.s.inta_map = 0; in octeon_pcie_setup()
2077 sli_ctl_portx.s.intb_map = 0; in octeon_pcie_setup()
2078 sli_ctl_portx.s.intc_map = 0; in octeon_pcie_setup()
2079 sli_ctl_portx.s.intd_map = 0; in octeon_pcie_setup()
2080 cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(!port), sli_ctl_portx.u64); in octeon_pcie_setup()