Lines Matching refs:insn
194 const struct bpf_insn *insn, in ebpf_to_mips_reg() argument
198 insn->src_reg : insn->dst_reg; in ebpf_to_mips_reg()
408 static void gen_imm_to_reg(const struct bpf_insn *insn, int reg, in gen_imm_to_reg() argument
411 if (insn->imm >= S16_MIN && insn->imm <= S16_MAX) { in gen_imm_to_reg()
412 emit_instr(ctx, addiu, reg, MIPS_R_ZERO, insn->imm); in gen_imm_to_reg()
414 int lower = (s16)(insn->imm & 0xffff); in gen_imm_to_reg()
415 int upper = insn->imm - lower; in gen_imm_to_reg()
422 static int gen_imm_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, in gen_imm_insn() argument
426 int dst = ebpf_to_mips_reg(ctx, insn, dst_reg); in gen_imm_insn()
431 switch (BPF_OP(insn->code)) { in gen_imm_insn()
462 if (BPF_CLASS(insn->code) == BPF_ALU64 && in gen_imm_insn()
463 BPF_OP(insn->code) != BPF_MOV && in gen_imm_insn()
464 get_reg_val_type(ctx, idx, insn->dst_reg) == REG_32BIT) in gen_imm_insn()
467 if (BPF_CLASS(insn->code) == BPF_ALU && in gen_imm_insn()
468 BPF_OP(insn->code) != BPF_LSH && in gen_imm_insn()
469 BPF_OP(insn->code) != BPF_MOV && in gen_imm_insn()
470 get_reg_val_type(ctx, idx, insn->dst_reg) != REG_32BIT) in gen_imm_insn()
473 if (insn->imm >= lower_bound && insn->imm <= upper_bound) { in gen_imm_insn()
475 switch (BPF_OP(insn->code) | BPF_CLASS(insn->code)) { in gen_imm_insn()
477 emit_instr(ctx, daddiu, dst, MIPS_R_ZERO, insn->imm); in gen_imm_insn()
481 emit_instr(ctx, andi, dst, dst, insn->imm); in gen_imm_insn()
485 emit_instr(ctx, ori, dst, dst, insn->imm); in gen_imm_insn()
489 emit_instr(ctx, xori, dst, dst, insn->imm); in gen_imm_insn()
492 emit_instr(ctx, daddiu, dst, dst, insn->imm); in gen_imm_insn()
495 emit_instr(ctx, daddiu, dst, dst, -insn->imm); in gen_imm_insn()
498 emit_instr(ctx, dsrl_safe, dst, dst, insn->imm & 0x3f); in gen_imm_insn()
501 emit_instr(ctx, srl, dst, dst, insn->imm & 0x1f); in gen_imm_insn()
504 emit_instr(ctx, dsll_safe, dst, dst, insn->imm & 0x3f); in gen_imm_insn()
507 emit_instr(ctx, sll, dst, dst, insn->imm & 0x1f); in gen_imm_insn()
510 emit_instr(ctx, dsra_safe, dst, dst, insn->imm & 0x3f); in gen_imm_insn()
513 emit_instr(ctx, sra, dst, dst, insn->imm & 0x1f); in gen_imm_insn()
516 emit_instr(ctx, addiu, dst, MIPS_R_ZERO, insn->imm); in gen_imm_insn()
519 emit_instr(ctx, addiu, dst, dst, insn->imm); in gen_imm_insn()
522 emit_instr(ctx, addiu, dst, dst, -insn->imm); in gen_imm_insn()
529 if (BPF_OP(insn->code) == BPF_MOV) { in gen_imm_insn()
530 gen_imm_to_reg(insn, dst, ctx); in gen_imm_insn()
532 gen_imm_to_reg(insn, MIPS_R_AT, ctx); in gen_imm_insn()
533 switch (BPF_OP(insn->code) | BPF_CLASS(insn->code)) { in gen_imm_insn()
659 static int build_one_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, in build_one_insn() argument
667 int bpf_op = BPF_OP(insn->code); in build_one_insn()
669 if (IS_ENABLED(CONFIG_32BIT) && ((BPF_CLASS(insn->code) == BPF_ALU64) in build_one_insn()
673 switch (insn->code) { in build_one_insn()
692 r = gen_imm_insn(insn, ctx, this_idx); in build_one_insn()
697 dst = ebpf_to_mips_reg(ctx, insn, dst_reg); in build_one_insn()
700 if (get_reg_val_type(ctx, this_idx, insn->dst_reg) == REG_32BIT) in build_one_insn()
702 if (insn->imm == 1) /* Mult by 1 is a nop */ in build_one_insn()
704 gen_imm_to_reg(insn, MIPS_R_AT, ctx); in build_one_insn()
713 dst = ebpf_to_mips_reg(ctx, insn, dst_reg); in build_one_insn()
716 if (get_reg_val_type(ctx, this_idx, insn->dst_reg) == REG_32BIT) in build_one_insn()
721 dst = ebpf_to_mips_reg(ctx, insn, dst_reg); in build_one_insn()
724 td = get_reg_val_type(ctx, this_idx, insn->dst_reg); in build_one_insn()
729 if (insn->imm == 1) /* Mult by 1 is a nop */ in build_one_insn()
731 gen_imm_to_reg(insn, MIPS_R_AT, ctx); in build_one_insn()
740 dst = ebpf_to_mips_reg(ctx, insn, dst_reg); in build_one_insn()
743 td = get_reg_val_type(ctx, this_idx, insn->dst_reg); in build_one_insn()
752 if (insn->imm == 0) in build_one_insn()
754 dst = ebpf_to_mips_reg(ctx, insn, dst_reg); in build_one_insn()
757 td = get_reg_val_type(ctx, this_idx, insn->dst_reg); in build_one_insn()
761 if (insn->imm == 1) { in build_one_insn()
767 gen_imm_to_reg(insn, MIPS_R_AT, ctx); in build_one_insn()
783 if (insn->imm == 0) in build_one_insn()
785 dst = ebpf_to_mips_reg(ctx, insn, dst_reg); in build_one_insn()
788 if (get_reg_val_type(ctx, this_idx, insn->dst_reg) == REG_32BIT) in build_one_insn()
790 if (insn->imm == 1) { in build_one_insn()
796 gen_imm_to_reg(insn, MIPS_R_AT, ctx); in build_one_insn()
822 src = ebpf_to_mips_reg(ctx, insn, src_reg); in build_one_insn()
823 dst = ebpf_to_mips_reg(ctx, insn, dst_reg); in build_one_insn()
826 if (get_reg_val_type(ctx, this_idx, insn->dst_reg) == REG_32BIT) in build_one_insn()
829 if (insn->src_reg == BPF_REG_10) { in build_one_insn()
837 } else if (get_reg_val_type(ctx, this_idx, insn->src_reg) == REG_32BIT) { in build_one_insn()
918 src = ebpf_to_mips_reg(ctx, insn, src_reg_no_fp); in build_one_insn()
919 dst = ebpf_to_mips_reg(ctx, insn, dst_reg); in build_one_insn()
922 td = get_reg_val_type(ctx, this_idx, insn->dst_reg); in build_one_insn()
928 ts = get_reg_val_type(ctx, this_idx, insn->src_reg); in build_one_insn()
1004 dst = ebpf_to_mips_reg(ctx, insn, dst_reg_fp_ok); in build_one_insn()
1007 if (insn->imm == 0) { in build_one_insn()
1010 gen_imm_to_reg(insn, MIPS_R_AT, ctx); in build_one_insn()
1025 src = ebpf_to_mips_reg(ctx, insn, src_reg_no_fp); in build_one_insn()
1026 dst = ebpf_to_mips_reg(ctx, insn, dst_reg); in build_one_insn()
1029 td = get_reg_val_type(ctx, this_idx, insn->dst_reg); in build_one_insn()
1030 ts = get_reg_val_type(ctx, this_idx, insn->src_reg); in build_one_insn()
1045 if ((insn + 1)->code == (BPF_JMP | BPF_EXIT) && insn->off == 1) { in build_one_insn()
1056 b_off = b_imm(this_idx + insn->off + 1, ctx); in build_one_insn()
1103 if ((insn + 1)->code == (BPF_JMP | BPF_EXIT) && insn->off == 1) { in build_one_insn()
1128 b_off = b_imm(this_idx + insn->off + 1, ctx); in build_one_insn()
1130 target = j_target(ctx, this_idx + insn->off + 1); in build_one_insn()
1156 dst = ebpf_to_mips_reg(ctx, insn, dst_reg_fp_ok); in build_one_insn()
1160 if (insn->imm == 0) { in build_one_insn()
1161 if ((insn + 1)->code == (BPF_JMP | BPF_EXIT) && insn->off == 1) { in build_one_insn()
1182 b_off = b_imm(this_idx + insn->off + 1, ctx); in build_one_insn()
1207 t64s = insn->imm + 1; in build_one_insn()
1209 t64s = insn->imm + 1; in build_one_insn()
1211 t64s = insn->imm; in build_one_insn()
1231 dst = ebpf_to_mips_reg(ctx, insn, dst_reg_fp_ok); in build_one_insn()
1239 t64s = (u64)(u32)(insn->imm) + 1; in build_one_insn()
1241 t64s = (u64)(u32)(insn->imm) + 1; in build_one_insn()
1243 t64s = (u64)(u32)(insn->imm); in build_one_insn()
1254 dst = ebpf_to_mips_reg(ctx, insn, dst_reg_fp_ok); in build_one_insn()
1258 if (ctx->use_bbit_insns && hweight32((u32)insn->imm) == 1) { in build_one_insn()
1259 if ((insn + 1)->code == (BPF_JMP | BPF_EXIT) && insn->off == 1) { in build_one_insn()
1263 emit_instr(ctx, bbit0, dst, ffs((u32)insn->imm) - 1, b_off); in build_one_insn()
1267 b_off = b_imm(this_idx + insn->off + 1, ctx); in build_one_insn()
1270 emit_instr(ctx, bbit1, dst, ffs((u32)insn->imm) - 1, b_off); in build_one_insn()
1274 t64 = (u32)insn->imm; in build_one_insn()
1287 b_off = b_imm(this_idx + insn->off + 1, ctx); in build_one_insn()
1289 target = j_target(ctx, this_idx + insn->off + 1); in build_one_insn()
1299 if (insn->src_reg != 0) in build_one_insn()
1301 dst = ebpf_to_mips_reg(ctx, insn, dst_reg); in build_one_insn()
1304 t64 = ((u64)(u32)insn->imm) | ((u64)(insn + 1)->imm << 32); in build_one_insn()
1310 t64s = (s64)insn->imm + (long)__bpf_call_base; in build_one_insn()
1324 dst = ebpf_to_mips_reg(ctx, insn, dst_reg); in build_one_insn()
1327 td = get_reg_val_type(ctx, this_idx, insn->dst_reg); in build_one_insn()
1328 if (insn->imm == 64 && td == REG_32BIT) in build_one_insn()
1331 if (insn->imm != 64 && td == REG_64BIT) { in build_one_insn()
1337 need_swap = (BPF_SRC(insn->code) == BPF_FROM_LE); in build_one_insn()
1339 need_swap = (BPF_SRC(insn->code) == BPF_FROM_BE); in build_one_insn()
1341 if (insn->imm == 16) { in build_one_insn()
1345 } else if (insn->imm == 32) { in build_one_insn()
1365 if (insn->dst_reg == BPF_REG_10) { in build_one_insn()
1368 mem_off = insn->off + MAX_BPF_STACK; in build_one_insn()
1370 dst = ebpf_to_mips_reg(ctx, insn, dst_reg); in build_one_insn()
1373 mem_off = insn->off; in build_one_insn()
1375 gen_imm_to_reg(insn, MIPS_R_AT, ctx); in build_one_insn()
1376 switch (BPF_SIZE(insn->code)) { in build_one_insn()
1396 if (insn->src_reg == BPF_REG_10) { in build_one_insn()
1399 mem_off = insn->off + MAX_BPF_STACK; in build_one_insn()
1401 src = ebpf_to_mips_reg(ctx, insn, src_reg_no_fp); in build_one_insn()
1404 mem_off = insn->off; in build_one_insn()
1406 dst = ebpf_to_mips_reg(ctx, insn, dst_reg); in build_one_insn()
1409 switch (BPF_SIZE(insn->code)) { in build_one_insn()
1431 if (insn->dst_reg == BPF_REG_10) { in build_one_insn()
1434 mem_off = insn->off + MAX_BPF_STACK; in build_one_insn()
1436 dst = ebpf_to_mips_reg(ctx, insn, dst_reg); in build_one_insn()
1439 mem_off = insn->off; in build_one_insn()
1441 src = ebpf_to_mips_reg(ctx, insn, src_reg_no_fp); in build_one_insn()
1444 if (BPF_MODE(insn->code) == BPF_XADD) { in build_one_insn()
1456 switch (BPF_SIZE(insn->code)) { in build_one_insn()
1458 if (get_reg_val_type(ctx, this_idx, insn->src_reg) == REG_32BIT) { in build_one_insn()
1473 if (get_reg_val_type(ctx, this_idx, insn->src_reg) == REG_32BIT) { in build_one_insn()
1486 switch (BPF_SIZE(insn->code)) { in build_one_insn()
1497 if (get_reg_val_type(ctx, this_idx, insn->src_reg) == REG_32BIT) { in build_one_insn()
1510 this_idx, (unsigned int)insn->code); in build_one_insn()
1524 const struct bpf_insn *insn; in build_int_body() local
1528 insn = prog->insnsi + i; in build_int_body()
1538 r = build_one_insn(insn, ctx, i, prog->len); in build_int_body()
1554 insn = prog->insnsi + i; in build_int_body()
1555 if (insn->code == (BPF_JMP | BPF_EXIT)) in build_int_body()
1566 const struct bpf_insn *insn; in reg_val_propagate_range() local
1574 insn = prog->insnsi + idx; in reg_val_propagate_range()
1575 switch (BPF_CLASS(insn->code)) { in reg_val_propagate_range()
1577 switch (BPF_OP(insn->code)) { in reg_val_propagate_range()
1589 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT); in reg_val_propagate_range()
1592 if (BPF_SRC(insn->code)) { in reg_val_propagate_range()
1593 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT); in reg_val_propagate_range()
1596 if (insn->imm >= 0) in reg_val_propagate_range()
1597 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS); in reg_val_propagate_range()
1599 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT); in reg_val_propagate_range()
1603 if (insn->imm == 64) in reg_val_propagate_range()
1604 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT); in reg_val_propagate_range()
1605 else if (insn->imm == 32) in reg_val_propagate_range()
1606 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT); in reg_val_propagate_range()
1608 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS); in reg_val_propagate_range()
1614 switch (BPF_OP(insn->code)) { in reg_val_propagate_range()
1616 if (BPF_SRC(insn->code)) { in reg_val_propagate_range()
1618 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT); in reg_val_propagate_range()
1621 if (insn->imm >= 0) in reg_val_propagate_range()
1622 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS); in reg_val_propagate_range()
1624 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT_32BIT); in reg_val_propagate_range()
1628 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT); in reg_val_propagate_range()
1633 switch (BPF_SIZE(insn->code)) { in reg_val_propagate_range()
1635 if (BPF_MODE(insn->code) == BPF_IMM) { in reg_val_propagate_range()
1638 val = (s64)((u32)insn->imm | ((u64)(insn + 1)->imm << 32)); in reg_val_propagate_range()
1640 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS); in reg_val_propagate_range()
1642 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT_32BIT); in reg_val_propagate_range()
1644 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT); in reg_val_propagate_range()
1648 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT); in reg_val_propagate_range()
1653 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS); in reg_val_propagate_range()
1656 if (BPF_MODE(insn->code) == BPF_IMM) in reg_val_propagate_range()
1657 set_reg_val_type(&exit_rvt, insn->dst_reg, in reg_val_propagate_range()
1658 insn->imm >= 0 ? REG_32BIT_POS : REG_32BIT); in reg_val_propagate_range()
1660 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT); in reg_val_propagate_range()
1666 switch (BPF_SIZE(insn->code)) { in reg_val_propagate_range()
1668 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT); in reg_val_propagate_range()
1672 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS); in reg_val_propagate_range()
1675 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT); in reg_val_propagate_range()
1681 switch (BPF_OP(insn->code)) { in reg_val_propagate_range()
1688 idx += insn->off; in reg_val_propagate_range()
1703 idx += insn->off; in reg_val_propagate_range()