Lines Matching +full:loongson +full:- +full:3
1 # SPDX-License-Identifier: GPL-2.0
125 bool "Generic board-agnostic MIPS kernel"
212 Support for the Texas Instruments AR7 System-on-a-Chip
283 Build a generic DT-based kernel image that boots on select
284 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
377 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
378 DECstation porting pages on <http://decstation.unix-ag.org/>.
417 Olivetti M700-10 workstations.
453 bool "Loongson 32-bit family of machines"
456 This enables support for the Loongson-1 family of machines.
458 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
463 bool "Loongson-2E/F family of machines"
466 This enables the support of early Loongson-2E/F family of machines.
469 bool "Loongson 64-bit family of machines"
504 This enables the support of Loongson-2/3 family of machines.
506 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
507 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
508 and Loongson-2F which will be removed), developed by the Institute
603 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
790 bool "Sibyte BCM91120C-CRhine"
799 bool "Sibyte BCM91120x-Carmel"
808 bool "Sibyte BCM91125C-CRhone"
818 bool "Sibyte BCM91125E-Rhone"
827 bool "Sibyte BCM91250A-SWARM"
840 bool "Sibyte BCM91250C2-LittleSur"
852 bool "Sibyte BCM91250E-Sentosa"
862 bool "Sibyte BCM91480B-BigSur"
911 The SNI RM200/300/400 are MIPS-based machines manufactured by
1053 source "arch/mips/sgi-ip27/Kconfig"
1057 source "arch/mips/cavium-octeon/Kconfig"
1370 bool "Loongson 64-bit CPU"
1391 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
1393 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
1394 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
1395 Loongson-2E/2F is not covered here and will be removed in future.
1398 bool "New Loongson-3 CPU Enhancements"
1402 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
1403 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
1404 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
1405 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
1409 time. If you want a generic kernel to run on all Loongson 3 machines,
1410 please say 'N' here. If you want a high-performance kernel to run on
1411 new Loongson-3 machines only, please say 'Y' here.
1414 bool "Old Loongson-3 LLSC Workarounds"
1418 Loongson-3 processors have the llsc issues which require workarounds.
1421 Newer Loongson-3 will fix these issues and no workarounds are needed.
1429 bool "Emulate the CPUCFG instruction on older Loongson cores"
1433 Loongson-3A R4 and newer have the CPUCFG instruction available for
1435 option provides emulation of the instruction on older Loongson
1436 cores, back to Loongson-3A1000.
1441 bool "Loongson 2E"
1445 The Loongson 2E processor implements the MIPS III instruction set
1452 bool "Loongson 2F"
1457 The Loongson 2F processor implements the MIPS III instruction set
1460 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
1465 bool "Loongson 1B"
1470 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
1475 bool "Loongson 1C"
1480 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
1492 MIPS32 architecture. Most modern embedded systems with a 32-bit
1511 MIPS32 architecture. Most modern embedded systems with a 32-bit
1557 MIPS64 architecture. Many modern embedded systems with a 64-bit
1578 MIPS64 architecture. Many modern embedded systems with a 64-bit
1633 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
1635 cache, IOCU/IOMMU (though might be unused depending on the system-
1678 MIPS Technologies R4000-series processors other than 4300, including
1696 MIPS Technologies R5000-series processors other than the Nevada.
1705 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
1715 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
1726 MIPS Technologies R10000-series processors.
1831 of lowmem (up to 3GB). If unsure, say 'N' here.
1857 64-bit addressing which in turn makes the PTEs 64-bit in size.
1868 bool "Loongson 2F Workarounds"
1873 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
1876 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
1878 Loongson 2F03 and later have fixed these issues and no workarounds
2064 # CPU may reorder R->R, R->W, W->R, W->W
2072 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
2171 actually benefits from 64-bit processing or if your machine has
2173 menu if your system does not support both 32-bit and 64-bit kernels.
2176 bool "32-bit kernel"
2180 Select this option if you want to build a 32-bit kernel.
2183 bool "64-bit kernel"
2186 Select this option if you want to build a 64-bit kernel.
2203 Set this to non-zero if building a guest kernel for KVM to skip RTC
2229 R3000-family processors this is the only available page size. Using
2249 all non-R3000 family processors. Note that you will need a suitable
2268 all non-R3000 family processor. Not that at the time of this
2305 # Support for a MIPS32 / MIPS64 style S-caches
2384 <http://www.imgtec.com/mips/mips-multithreading.asp>.
2405 bool "Dynamic FPU affinity for FP-intensive threads"
2410 bool "MIPS R2-to-R6 emulator"
2415 Choose this option if you want to run non-R6 MIPS userland code.
2418 The only reason this is a build-time option is to save ~14K from the
2614 # CPU non-features
2649 # interrupts during indexed I-cache flushes seems to be sufficient to deal
2701 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
2703 # I-cache line worth of instructions being fetched may case spurious
2709 # may cause ll / sc and lld / scd sequences to execute non-atomically.
2718 # - Highmem only makes sense for the 32-bit kernel.
2719 # - The current highmem code will only work properly on physically indexed
2726 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
2749 This option must be set if a kernel might be executed on a MIPS16-
2751 words, it makes the kernel MIPS16-tolerant.
2768 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
2841 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
2842 EVA or 64-bit. The default is 16Mb.
2869 bool "Multi-Processing support"
2876 If you say N here, the kernel will run on uni- and multiprocessor
2885 See also the SMP-HOWTO available at
2891 bool "Support for hot-pluggable CPUs"
2928 int "Maximum number of CPUs (2-256)"
2938 kernel will support. The maximum supported value is 32 for 32-bit
2939 kernel and 64 for 64-bit kernels; the minimum value which makes
2943 This is purely to save memory - each supported CPU adds
3067 which are loaded in the main kernel with kexec-tools into
3082 passed to the panic-ed kernel).
3085 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
3088 When this is enabled, the kernel will support use of 64-bit floating
3090 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
3091 32-bit MIPS systems this support is at the cost of increasing the
3094 will require 64-bit floating point, you may wish to reduce the size
3136 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
3196 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
3230 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
3232 <http://www.linux-mips.org/wiki/DECstation>
3287 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
3301 64-bit binaries using 32-bit quantities for addressing and certain
3302 data that would normally be 64-bit. They are used in special