97 #define A64_ADDSUB_IMM(sf, Rd, Rn, imm12, type) \  argument
98 	aarch64_insn_gen_add_sub_imm(Rd, Rn, imm12, \
101 #define A64_ADD_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, ADD)  argument
102 #define A64_SUB_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, SUB)  argument
103 #define A64_ADDS_I(sf, Rd, Rn, imm12) \  argument
104 	A64_ADDSUB_IMM(sf, Rd, Rn, imm12, ADD_SETFLAGS)
105 #define A64_SUBS_I(sf, Rd, Rn, imm12) \  argument
106 	A64_ADDSUB_IMM(sf, Rd, Rn, imm12, SUB_SETFLAGS)
112 #define A64_MOV(sf, Rd, Rn) A64_ADD_I(sf, Rd, Rn, 0)  argument
115 #define A64_BITFIELD(sf, Rd, Rn, immr, imms, type) \  argument
116 	aarch64_insn_gen_bitfield(Rd, Rn, immr, imms, \
119 #define A64_SBFM(sf, Rd, Rn, ir, is) A64_BITFIELD(sf, Rd, Rn, ir, is, SIGNED)  argument
121 #define A64_UBFM(sf, Rd, Rn, ir, is) A64_BITFIELD(sf, Rd, Rn, ir, is, UNSIGNED)  argument
124 #define A64_LSL(sf, Rd, Rn, shift) ({	\  argument
126 	A64_UBFM(sf, Rd, Rn, (unsigned)-(shift) % sz, sz - 1 - (shift)); \
129 #define A64_LSR(sf, Rd, Rn, shift) A64_UBFM(sf, Rd, Rn, shift, (sf) ? 63 : 31)  argument
131 #define A64_ASR(sf, Rd, Rn, shift) A64_SBFM(sf, Rd, Rn, shift, (sf) ? 63 : 31)  argument
134 #define A64_UXTH(sf, Rd, Rn) A64_UBFM(sf, Rd, Rn, 0, 15)  argument
135 #define A64_UXTW(sf, Rd, Rn) A64_UBFM(sf, Rd, Rn, 0, 31)  argument
138 #define A64_MOVEW(sf, Rd, imm16, shift, type) \  argument
139 	aarch64_insn_gen_movewide(Rd, imm16, shift, \
144 #define A64_MOVN(sf, Rd, imm16, shift) A64_MOVEW(sf, Rd, imm16, shift, INVERSE)  argument
145 #define A64_MOVZ(sf, Rd, imm16, shift) A64_MOVEW(sf, Rd, imm16, shift, ZERO)  argument
146 #define A64_MOVK(sf, Rd, imm16, shift) A64_MOVEW(sf, Rd, imm16, shift, KEEP)  argument
149 #define A64_ADDSUB_SREG(sf, Rd, Rn, Rm, type) \  argument
150 	aarch64_insn_gen_add_sub_shifted_reg(Rd, Rn, Rm, 0, \
153 #define A64_ADD(sf, Rd, Rn, Rm)  A64_ADDSUB_SREG(sf, Rd, Rn, Rm, ADD)  argument
154 #define A64_SUB(sf, Rd, Rn, Rm)  A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB)  argument
155 #define A64_SUBS(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB_SETFLAGS)  argument
157 #define A64_NEG(sf, Rd, Rm) A64_SUB(sf, Rd, A64_ZR, Rm)  argument
162 #define A64_DATA1(sf, Rd, Rn, type) aarch64_insn_gen_data1(Rd, Rn, \  argument
165 #define A64_REV16(sf, Rd, Rn) A64_DATA1(sf, Rd, Rn, REVERSE_16)  argument
166 #define A64_REV32(sf, Rd, Rn) A64_DATA1(sf, Rd, Rn, REVERSE_32)  argument
167 #define A64_REV64(Rd, Rn)     A64_DATA1(1, Rd, Rn, REVERSE_64)  argument
171 #define A64_DATA2(sf, Rd, Rn, Rm, type) aarch64_insn_gen_data2(Rd, Rn, Rm, \  argument
173 #define A64_UDIV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, UDIV)  argument
174 #define A64_LSLV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSLV)  argument
175 #define A64_LSRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSRV)  argument
176 #define A64_ASRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, ASRV)  argument
180 #define A64_MADD(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \  argument
183 #define A64_MSUB(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \  argument
186 #define A64_MUL(sf, Rd, Rn, Rm) A64_MADD(sf, Rd, A64_ZR, Rn, Rm)  argument
189 #define A64_LOGIC_SREG(sf, Rd, Rn, Rm, type) \  argument
190 	aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
193 #define A64_AND(sf, Rd, Rn, Rm)  A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND)  argument
194 #define A64_ORR(sf, Rd, Rn, Rm)  A64_LOGIC_SREG(sf, Rd, Rn, Rm, ORR)  argument
195 #define A64_EOR(sf, Rd, Rn, Rm)  A64_LOGIC_SREG(sf, Rd, Rn, Rm, EOR)  argument
196 #define A64_ANDS(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND_SETFLAGS)  argument
201 #define A64_LOGIC_IMM(sf, Rd, Rn, imm, type) ({ \  argument
204 		A64_VARIANT(sf), Rn, Rd, imm64); \
207 #define A64_AND_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, AND)  argument
208 #define A64_ORR_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, ORR)  argument
209 #define A64_EOR_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, EOR)  argument
210 #define A64_ANDS_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, AND_SETFLAGS)  argument