arm64/kvm/sys_regs.c

49 		(u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2)
742 	if (r->CRn == 9 && r->CRm == 13) {  in access_pmu_evcntr()
757 	} else if (r->CRn == 0 && r->CRm == 9) {  in access_pmu_evcntr()
763 	} else if (r->CRn == 14 && (r->CRm & 12) == 8) {  in access_pmu_evcntr()
797 	if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {  in access_pmu_evtyper()
801 	} else if (r->CRn == 14 && (r->CRm & 12) == 12) {  in access_pmu_evtyper()
1318 	Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2),	\
1767 	{ AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1769 	{ Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n },	      \
1771 	{ Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n },	      \
1773 	{ Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1776 	{ AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n }
1785 	{ Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr },
1787 	{ Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1791 	{ Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1794 	{ Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 },
1796 	{ Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 },
1799 	{ Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1801 	{ Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1806 	{ Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1808 	{ Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1811 	{ Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 },
1823 	{ Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1827 	{ Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1830 	{ Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1834 	{ Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1837 	{ Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1851 	{ Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1854 	{ Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1856 	{ Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1858 	{ Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1860 	{ Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1862 	{ Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1864 	{ Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
1879 	{ Op1(0), CRn(0b1110),						\
1886 	{ Op1(0), CRn(0b1110),						\
1896 	{ Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
1897 	{ Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 },
1899 	{ AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 },
1901 	{ AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 },
1902 	{ Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
1903 	{ Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 },
1905 	{ AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 },
1907 	{ AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 },
1908 	{ Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 },
1910 	{ Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 },
1911 	{ Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 },
1913 	{ Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 },
1915 	{ Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 },
1917 	{ AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 },
1919 	{ AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 },
1924 	{ Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
1925 	{ Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
1926 	{ Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
1929 	{ Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
1930 	{ Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
1931 	{ Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
1932 	{ Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
1933 	{ Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
1934 	{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
1935 	{ AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
1936 	{ AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
1937 	{ Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
1938 	{ Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
1939 	{ Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
1940 	{ Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
1941 	{ Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
1942 	{ Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
1943 	{ Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
1944 	{ AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 4), access_pmceid },
1945 	{ AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 5), access_pmceid },
1947 	{ Op1( 0), CRn( 9), CRm(14), Op2( 6), trap_raz_wi },
1950 	{ AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },
1952 	{ AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 },
1954 	{ AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 },
1956 	{ AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 },
1959 	{ Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
1961 	{ Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 },
2032 	{ Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
2034 	{ Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
2035 	{ Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
2036 	{ Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 },
2040 	{ Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
2041 	{ Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
2042 	{ Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
2043 	{ Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 },
2044 	{ Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
2045 	{ Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
2193 	params.CRn = 0;  in kvm_handle_cp_64()
2239 	params.CRn = (esr >> 10) & 0xf;  in kvm_handle_cp_32()
2277 	return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011;  in is_imp_def_sys_reg()
2331 	params.CRn = (esr >> 10) & 0xf;  in kvm_handle_sys_reg()
2365 		params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)  in index_to_params()
2660 		(reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |  in sys_reg_to_index()