include/asm/esr.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Copyright (C) 2013 - ARM Ltd
23 /* Unallocated EC: 0x0A - 0x0B */
27 /* Unallocated EC: 0x0F - 0x10 */
40 /* Unallocated EC: 0x1D - 0x1E */
51 /* Unallocated EC: 0x29 - 0x2B */
53 /* Unallocated EC: 0x2D - 0x2E */
61 /* Unallocated EC: 0x36 - 0x37 */
67 /* Unallocated EC: 0x3D - 0x3F */
72 #define ESR_ELx_EC_MASK		(UL(0x3F) << ESR_ELx_EC_SHIFT)
76 #define ESR_ELx_IL		(UL(1) << ESR_ELx_IL_SHIFT)
77 #define ESR_ELx_ISS_MASK	(ESR_ELx_IL - 1)
81 #define ESR_ELx_WNR		(UL(1) << ESR_ELx_WNR_SHIFT)
85 #define ESR_ELx_IDS		(UL(1) << ESR_ELx_IDS_SHIFT)
87 #define ESR_ELx_AET		(UL(0x7) << ESR_ELx_AET_SHIFT)
89 #define ESR_ELx_AET_UC		(UL(0) << ESR_ELx_AET_SHIFT)
90 #define ESR_ELx_AET_UEU		(UL(1) << ESR_ELx_AET_SHIFT)
91 #define ESR_ELx_AET_UEO		(UL(2) << ESR_ELx_AET_SHIFT)
92 #define ESR_ELx_AET_UER		(UL(3) << ESR_ELx_AET_SHIFT)
93 #define ESR_ELx_AET_CE		(UL(6) << ESR_ELx_AET_SHIFT)
97 #define ESR_ELx_SET_MASK	(UL(3) << ESR_ELx_SET_SHIFT)
99 #define ESR_ELx_FnV		(UL(1) << ESR_ELx_FnV_SHIFT)
101 #define ESR_ELx_EA		(UL(1) << ESR_ELx_EA_SHIFT)
103 #define ESR_ELx_S1PTW		(UL(1) << ESR_ELx_S1PTW_SHIFT)
119 #define ESR_ELx_ISV		(UL(1) << ESR_ELx_ISV_SHIFT)
121 #define ESR_ELx_SAS		(UL(3) << ESR_ELx_SAS_SHIFT)
123 #define ESR_ELx_SSE		(UL(1) << ESR_ELx_SSE_SHIFT)
125 #define ESR_ELx_SRT_MASK	(UL(0x1F) << ESR_ELx_SRT_SHIFT)
127 #define ESR_ELx_SF 		(UL(1) << ESR_ELx_SF_SHIFT)
129 #define ESR_ELx_AR 		(UL(1) << ESR_ELx_AR_SHIFT)
131 #define ESR_ELx_CM 		(UL(1) << ESR_ELx_CM_SHIFT)
134 #define ESR_ELx_CV		(UL(1) << 24)
136 #define ESR_ELx_COND_MASK	(UL(0xF) << ESR_ELx_COND_SHIFT)
137 #define ESR_ELx_WFx_ISS_TI	(UL(1) << 0)
138 #define ESR_ELx_WFx_ISS_WFI	(UL(0) << 0)
139 #define ESR_ELx_WFx_ISS_WFE	(UL(1) << 0)
140 #define ESR_ELx_xVC_IMM_MASK	((1UL << 16) - 1)
142 #define DISR_EL1_IDS		(UL(1) << 24)
159 #define ESR_ELx_SYS64_ISS_RES0_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
165 #define ESR_ELx_SYS64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
166 #define ESR_ELx_SYS64_ISS_CRM_SHIFT	1
167 #define ESR_ELx_SYS64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
169 #define ESR_ELx_SYS64_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
171 #define ESR_ELx_SYS64_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
173 #define ESR_ELx_SYS64_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
175 #define ESR_ELx_SYS64_ISS_OP0_MASK	(UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
195  * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0)
210 				(ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
215  * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
225 #define ESR_ELx_SYS64_ISS_SYS_CTR	ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
259  * ISS field definitions for floating-point exception traps
265 #define ESR_ELx_FP_EXC_TFV	(UL(1) << 23)
275 #define ESR_ELx_CP15_32_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
276 #define ESR_ELx_CP15_32_ISS_CRM_SHIFT	1
277 #define ESR_ELx_CP15_32_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
279 #define ESR_ELx_CP15_32_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
281 #define ESR_ELx_CP15_32_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
283 #define ESR_ELx_CP15_32_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
301 #define ESR_ELx_CP15_64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
304 #define ESR_ELx_CP15_64_ISS_RT2_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
307 #define ESR_ELx_CP15_64_ISS_OP1_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
308 #define ESR_ELx_CP15_64_ISS_CRM_SHIFT	1
309 #define ESR_ELx_CP15_64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
319 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCT	(ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \