Lines Matching refs:x0
20 mov_q x0, INIT_SCTLR_EL2_MMU_OFF
21 msr sctlr_el2, x0
36 mrs x0, cnthctl_el2
37 orr x0, x0, #3 // Enable EL1 physical timers
38 msr cnthctl_el2, x0
44 sbfx x0, x1, #ID_AA64DFR0_PMUVER_SHIFT, #4
45 cmp x0, #1
47 mrs x0, pmcr_el0 // Disable debug access traps
48 ubfx x0, x0, #11, #5 // to EL2 and allow access to
50 csel x2, xzr, x0, lt // all PMU counters from EL1
53 ubfx x0, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4
54 cbz x0, .Lskip_spe_\@ // Skip if SPE not present
56 mrs_s x0, SYS_PMBIDR_EL1 // If SPE available at EL2,
57 and x0, x0, #(1 << SYS_PMBIDR_EL1_P_SHIFT)
58 cbnz x0, .Lskip_spe_el2_\@ // then permit sampling of physical
59 mov x0, #(1 << SYS_PMSCR_EL2_PCT_SHIFT | \
61 msr_s SYS_PMSCR_EL2, x0 // addresses and physical counter
63 mov x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)
64 orr x2, x2, x0 // If we don't have VHE, then
69 ubfx x0, x1, #ID_AA64DFR0_TRBE_SHIFT, #4
70 cbz x0, .Lskip_trace_\@ // Skip if TraceBuffer is not present
72 mrs_s x0, SYS_TRBIDR_EL1
73 and x0, x0, TRBIDR_PROG
74 cbnz x0, .Lskip_trace_\@ // If TRBE is available at EL2
76 mov x0, #(MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT)
77 orr x2, x2, x0 // allow the EL1&0 translation
87 ubfx x0, x1, #ID_AA64MMFR1_LOR_SHIFT, 4
88 cbz x0, .Lskip_lor_\@
100 mrs x0, id_aa64pfr0_el1
101 ubfx x0, x0, #ID_AA64PFR0_GIC_SHIFT, #4
102 cbz x0, .Lskip_gicv3_\@
104 mrs_s x0, SYS_ICC_SRE_EL2
105 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
106 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
107 msr_s SYS_ICC_SRE_EL2, x0
109 mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back,
110 tbz x0, #0, .Lskip_gicv3_\@ // and check that it sticks
121 mrs x0, midr_el1
123 msr vpidr_el2, x0
129 mov x0, #0x33ff
130 msr cptr_el2, x0 // Disable copro. traps to EL2
139 bic x0, x0, #CPTR_EL2_TZ // Also disable SVE traps
140 msr cptr_el2, x0 // Disable copro. traps to EL2
148 mov x0, #INIT_PSTATE_EL1
149 msr spsr_el2, x0