dts/toshiba/tmpv7708.dtsi

13 /memreserve/ 0x81000000 0x00300000;	/* cpu-release-addr */
22 		#size-cells = <0>;
56 		cpu0: cpu@0 {
60 			cpu-release-addr = <0x0 0x81100000>;
61 			reg = <0x00>;
68 			cpu-release-addr = <0x0 0x81100000>;
69 			reg = <0x01>;
76 			cpu-release-addr = <0x0 0x81100000>;
77 			reg = <0x02>;
84 			cpu-release-addr = <0x0 0x81100000>;
85 			reg = <0x03>;
92 			cpu-release-addr = <0x0 0x81100000>;
93 			reg = <0x100>;
100 			cpu-release-addr = <0x0 0x81100000>;
101 			reg = <0x101>;
108 			cpu-release-addr = <0x0 0x81100000>;
109 			reg = <0x102>;
116 			cpu-release-addr = <0x0 0x81100000>;
117 			reg = <0x103>;
134 		#clock-cells = <0>;
149 			reg = <0 0x24001000 0 0x1000>,
150 			      <0 0x24002000 0 0x2000>,
151 			      <0 0x24004000 0 0x2000>,
152 			      <0 0x24006000 0 0x2000>;
157 			reg = <0 0x24190000 0 0x10000>;
162 			reg = <0 0x28200000 0 0x1000>;
165 			pinctrl-0 = <&uart0_pins>;
171 			reg = <0 0x28201000 0 0x1000>;
174 			pinctrl-0 = <&uart1_pins>;
180 			reg = <0 0x28202000 0 0x1000>;
183 			pinctrl-0 = <&uart2_pins>;
189 			reg = <0 0x28203000 0 0x1000>;
192 			pinctrl-0 = <&uart3_pins>;
198 			reg = <0 0x28030000 0 0x1000>;
201 			pinctrl-0 = <&i2c0_pins>;
204 			#size-cells = <0>;
210 			reg = <0 0x28031000 0 0x1000>;
213 			pinctrl-0 = <&i2c1_pins>;
216 			#size-cells = <0>;
222 			reg = <0 0x28032000 0 0x1000>;
225 			pinctrl-0 = <&i2c2_pins>;
228 			#size-cells = <0>;
234 			reg = <0 0x28033000 0 0x1000>;
237 			pinctrl-0 = <&i2c3_pins>;
240 			#size-cells = <0>;
246 			reg = <0 0x28034000 0 0x1000>;
249 			pinctrl-0 = <&i2c4_pins>;
252 			#size-cells = <0>;
258 			reg = <0 0x28035000 0 0x1000>;
261 			pinctrl-0 = <&i2c5_pins>;
264 			#size-cells = <0>;
270 			reg = <0 0x28036000 0 0x1000>;
273 			pinctrl-0 = <&i2c6_pins>;
276 			#size-cells = <0>;
282 			reg = <0 0x28037000 0 0x1000>;
285 			pinctrl-0 = <&i2c7_pins>;
288 			#size-cells = <0>;
294 			reg = <0 0x28038000 0 0x1000>;
297 			pinctrl-0 = <&i2c8_pins>;
300 			#size-cells = <0>;
306 			reg = <0 0x28140000 0 0x1000>;
309 			pinctrl-0 = <&spi0_pins>;
312 			#size-cells = <0>;
318 			reg = <0 0x28141000 0 0x1000>;
321 			pinctrl-0 = <&spi1_pins>;
324 			#size-cells = <0>;
330 			reg = <0 0x28142000 0 0x1000>;
333 			pinctrl-0 = <&spi2_pins>;
336 			#size-cells = <0>;
342 			reg = <0 0x28143000 0 0x1000>;
345 			pinctrl-0 = <&spi3_pins>;
348 			#size-cells = <0>;
354 			reg = <0 0x28144000 0 0x1000>;
357 			pinctrl-0 = <&spi4_pins>;
360 			#size-cells = <0>;
366 			reg = <0 0x28145000 0 0x1000>;
369 			pinctrl-0 = <&spi5_pins>;
372 			#size-cells = <0>;
378 			reg = <0 0x28146000 0 0x1000>;
381 			pinctrl-0 = <&spi6_pins>;
384 			#size-cells = <0>;