dts/ti/k3-j721e-main.dtsi

13 		#clock-cells = <0>;
15 		clock-frequency = <0>;
19 		#clock-cells = <0>;
21 		clock-frequency = <0>;
28 		reg = <0x0 0x70000000 0x0 0x800000>;
31 		ranges = <0x0 0x0 0x70000000 0x800000>;
33 		atf-sram@0 {
34 			reg = <0x0 0x20000>;
40 		reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
43 		ranges = <0x0 0x0 0x00100000 0x1c000>;
47 			reg = <0x00004070 0x4>;
50 			ranges = <0x4070 0x4070 0x4>;
55 			reg = <0x00004074 0x4>;
58 			ranges = <0x4074 0x4074 0x4>;
63 			reg = <0x00004078 0x4>;
66 			ranges = <0x4078 0x4078 0x4>;
71 			reg = <0x0000407c 0x4>;
74 			ranges = <0x407c 0x407c 0x4>;
79 			reg = <0x00004080 0x50>;
81 			mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
82 					<0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
83 					<0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
84 					<0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
85 					<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
98 			mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
99 					<0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
110 		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
111 		      <0x00 0x01900000 0x00 0x100000>,	/* GICR */
112 		      <0x00 0x6f000000 0x00 0x2000>,	/* GICC */
113 		      <0x00 0x6f010000 0x00 0x1000>,	/* GICH */
114 		      <0x00 0x6f020000 0x00 0x2000>;	/* GICV */
121 			reg = <0x00 0x01820000 0x00 0x10000>;
122 			socionext,synquacer-pre-its = <0x1000000 0x400000>;
157 			ti,interrupt-ranges = <0 64 64>,
164 			reg = <0x0 0x33d00000 0x0 0x100000>;
170 			ti,interrupt-ranges = <0 0 256>;
177 			reg = <0x00 0x32c00000 0x00 0x100000>,
178 			      <0x00 0x32400000 0x00 0x100000>,
179 			      <0x00 0x32800000 0x00 0x100000>;
186 			reg = <0x0 0x36600000 0x0 0x100000>;
196 			reg = <0x00 0x30e00000 0x00 0x1000>;
202 			reg = <0x00 0x31f80000 0x00 0x200>;
211 			reg = <0x00 0x31f81000 0x00 0x200>;
220 			reg = <0x00 0x31f82000 0x00 0x200>;
229 			reg = <0x00 0x31f83000 0x00 0x200>;
238 			reg = <0x00 0x31f84000 0x00 0x200>;
247 			reg = <0x00 0x31f85000 0x00 0x200>;
256 			reg = <0x00 0x31f86000 0x00 0x200>;
265 			reg = <0x00 0x31f87000 0x00 0x200>;
274 			reg = <0x00 0x31f88000 0x00 0x200>;
283 			reg = <0x00 0x31f89000 0x00 0x200>;
292 			reg = <0x00 0x31f8a000 0x00 0x200>;
301 			reg = <0x00 0x31f8b000 0x00 0x200>;
310 			reg =	<0x0 0x3c000000 0x0 0x400000>,
311 				<0x0 0x38000000 0x0 0x400000>,
312 				<0x0 0x31120000 0x0 0x100>,
313 				<0x0 0x33000000 0x0 0x40000>;
316 			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
324 			reg =	<0x0 0x31150000 0x0 0x100>,
325 				<0x0 0x34000000 0x0 0x100000>,
326 				<0x0 0x35000000 0x0 0x100000>;
335 			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
336 						<0x0f>, /* TX_HCHAN */
337 						<0x10>; /* TX_UHCHAN */
338 			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
339 						<0x0b>, /* RX_HCHAN */
340 						<0x0c>; /* RX_UHCHAN */
341 			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
346 			reg = <0x0 0x310d0000 0x0 0x400>;
359 		reg = <0x0 0x4e00000 0x0 0x1200>;
363 		ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
367 		dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
368 				<&main_udmap 0x4001>;
374 			reg = <0x0 0x4e10000 0x0 0x7d>;
382 		/* Proxy 0 addressing */
383 		reg = <0x0 0x11c000 0x0 0x2b4>;
386 		pinctrl-single,function-mask = <0xffffffff>;
396 		assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
400 		ranges = <0x5000000 0x0 0x5000000 0x10000>;
404 			#clock-cells = <0>;
410 			clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
411 			#clock-cells = <0>;
413 			assigned-clock-parents = <&k3_clks 292 0>;
417 			clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
418 			#clock-cells = <0>;
425 			#clock-cells = <0>;
430 			#clock-cells = <0>;
436 			reg = <0x5000000 0x10000>;
438 			#size-cells = <0>;
439 			resets = <&serdes_wiz0 0>;
453 		assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
457 		ranges = <0x5010000 0x0 0x5010000 0x10000>;
461 			#clock-cells = <0>;
467 			clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
468 			#clock-cells = <0>;
470 			assigned-clock-parents = <&k3_clks 293 0>;
474 			clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
475 			#clock-cells = <0>;
482 			#clock-cells = <0>;
487 			#clock-cells = <0>;
493 			reg = <0x5010000 0x10000>;
495 			#size-cells = <0>;
496 			resets = <&serdes_wiz1 0>;
510 		assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
514 		ranges = <0x5020000 0x0 0x5020000 0x10000>;
518 			#clock-cells = <0>;
524 			clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
525 			#clock-cells = <0>;
527 			assigned-clock-parents = <&k3_clks 294 0>;
531 			clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
532 			#clock-cells = <0>;
539 			#clock-cells = <0>;
544 			#clock-cells = <0>;
550 			reg = <0x5020000 0x10000>;
552 			#size-cells = <0>;
553 			resets = <&serdes_wiz2 0>;
567 		assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
571 		ranges = <0x5030000 0x0 0x5030000 0x10000>;
575 			#clock-cells = <0>;
581 			clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
582 			#clock-cells = <0>;
584 			assigned-clock-parents = <&k3_clks 295 0>;
588 			clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
589 			#clock-cells = <0>;
596 			#clock-cells = <0>;
601 			#clock-cells = <0>;
607 			reg = <0x5030000 0x10000>;
609 			#size-cells = <0>;
610 			resets = <&serdes_wiz3 0>;
619 		reg = <0x00 0x02900000 0x00 0x1000>,
620 		      <0x00 0x02907000 0x00 0x400>,
621 		      <0x00 0x0d000000 0x00 0x00800000>,
622 		      <0x00 0x10000000 0x00 0x00001000>;
635 		bus-range = <0x0 0xff>;
636 		vendor-id = <0x104c>;
637 		device-id = <0xb00d>;
638 		msi-map = <0x0 &gic_its 0x0 0x10000>;
640 		ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
641 			 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
642 		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
647 		reg = <0x00 0x02900000 0x00 0x1000>,
648 		      <0x00 0x02907000 0x00 0x400>,
649 		      <0x00 0x0d000000 0x00 0x00800000>,
650 		      <0x00 0x10000000 0x00 0x08000000>;
662 		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
668 		reg = <0x00 0x02910000 0x00 0x1000>,
669 		      <0x00 0x02917000 0x00 0x400>,
670 		      <0x00 0x0d800000 0x00 0x00800000>,
671 		      <0x00 0x18000000 0x00 0x00001000>;
684 		bus-range = <0x0 0xff>;
685 		vendor-id = <0x104c>;
686 		device-id = <0xb00d>;
687 		msi-map = <0x0 &gic_its 0x10000 0x10000>;
689 		ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
690 			 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
691 		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
696 		reg = <0x00 0x02910000 0x00 0x1000>,
697 		      <0x00 0x02917000 0x00 0x400>,
698 		      <0x00 0x0d800000 0x00 0x00800000>,
699 		      <0x00 0x18000000 0x00 0x08000000>;
711 		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
717 		reg = <0x00 0x02920000 0x00 0x1000>,
718 		      <0x00 0x02927000 0x00 0x400>,
719 		      <0x00 0x0e000000 0x00 0x00800000>,
720 		      <0x44 0x00000000 0x00 0x00001000>;
733 		bus-range = <0x0 0xff>;
734 		vendor-id = <0x104c>;
735 		device-id = <0xb00d>;
736 		msi-map = <0x0 &gic_its 0x20000 0x10000>;
738 		ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
739 			 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
740 		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
745 		reg = <0x00 0x02920000 0x00 0x1000>,
746 		      <0x00 0x02927000 0x00 0x400>,
747 		      <0x00 0x0e000000 0x00 0x00800000>,
748 		      <0x44 0x00000000 0x00 0x08000000>;
760 		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
766 		reg = <0x00 0x02930000 0x00 0x1000>,
767 		      <0x00 0x02937000 0x00 0x400>,
768 		      <0x00 0x0e800000 0x00 0x00800000>,
769 		      <0x44 0x10000000 0x00 0x00001000>;
782 		bus-range = <0x0 0xff>;
783 		vendor-id = <0x104c>;
784 		device-id = <0xb00d>;
785 		msi-map = <0x0 &gic_its 0x30000 0x10000>;
787 		ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
788 			 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
789 		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
794 		reg = <0x00 0x02930000 0x00 0x1000>,
795 		      <0x00 0x02937000 0x00 0x400>,
796 		      <0x00 0x0e800000 0x00 0x00800000>,
797 		      <0x44 0x10000000 0x00 0x08000000>;
809 		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
817 		reg = <0x00 0x02800000 0x00 0x100>;
824 		clocks = <&k3_clks 146 0>;
830 		reg = <0x00 0x02810000 0x00 0x100>;
837 		clocks = <&k3_clks 278 0>;
843 		reg = <0x00 0x02820000 0x00 0x100>;
850 		clocks = <&k3_clks 279 0>;
856 		reg = <0x00 0x02830000 0x00 0x100>;
863 		clocks = <&k3_clks 280 0>;
869 		reg = <0x00 0x02840000 0x00 0x100>;
876 		clocks = <&k3_clks 281 0>;
882 		reg = <0x00 0x02850000 0x00 0x100>;
889 		clocks = <&k3_clks 282 0>;
895 		reg = <0x00 0x02860000 0x00 0x100>;
902 		clocks = <&k3_clks 283 0>;
908 		reg = <0x00 0x02870000 0x00 0x100>;
915 		clocks = <&k3_clks 284 0>;
921 		reg = <0x00 0x02880000 0x00 0x100>;
928 		clocks = <&k3_clks 285 0>;
934 		reg = <0x00 0x02890000 0x00 0x100>;
941 		clocks = <&k3_clks 286 0>;
947 		reg = <0x0 0x00600000 0x0 0x100>;
956 		ti,davinci-gpio-unbanked = <0>;
958 		clocks = <&k3_clks 105 0>;
964 		reg = <0x0 0x00601000 0x0 0x100>;
972 		ti,davinci-gpio-unbanked = <0>;
974 		clocks = <&k3_clks 106 0>;
980 		reg = <0x0 0x00610000 0x0 0x100>;
989 		ti,davinci-gpio-unbanked = <0>;
991 		clocks = <&k3_clks 107 0>;
997 		reg = <0x0 0x00611000 0x0 0x100>;
1005 		ti,davinci-gpio-unbanked = <0>;
1007 		clocks = <&k3_clks 108 0>;
1013 		reg = <0x0 0x00620000 0x0 0x100>;
1022 		ti,davinci-gpio-unbanked = <0>;
1024 		clocks = <&k3_clks 109 0>;
1030 		reg = <0x0 0x00621000 0x0 0x100>;
1038 		ti,davinci-gpio-unbanked = <0>;
1040 		clocks = <&k3_clks 110 0>;
1046 		reg = <0x0 0x00630000 0x0 0x100>;
1055 		ti,davinci-gpio-unbanked = <0>;
1057 		clocks = <&k3_clks 111 0>;
1063 		reg = <0x0 0x00631000 0x0 0x100>;
1071 		ti,davinci-gpio-unbanked = <0>;
1073 		clocks = <&k3_clks 112 0>;
1079 		reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
1083 		clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;
1089 		ti,otap-del-sel = <0x2>;
1090 		ti,trm-icp = <0x8>;
1091 		ti,strobe-sel = <0x77>;
1097 		reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
1101 		clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
1102 		assigned-clocks = <&k3_clks 92 0>;
1104 		ti,otap-del-sel = <0x2>;
1105 		ti,trm-icp = <0x8>;
1106 		ti,clkbuf-sel = <0x7>;
1113 		reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
1117 		clocks = <&k3_clks 93 0>, <&k3_clks 93 5>;
1118 		assigned-clocks = <&k3_clks 93 0>;
1120 		ti,otap-del-sel = <0x2>;
1121 		ti,trm-icp = <0x8>;
1122 		ti,clkbuf-sel = <0x7>;
1129 		reg = <0x00 0x4104000 0x00 0x100>;
1142 			reg = <0x00 0x6000000 0x00 0x10000>,
1143 			      <0x00 0x6010000 0x00 0x10000>,
1144 			      <0x00 0x6020000 0x00 0x10000>;
1146 			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
1148 				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
1159 		reg = <0x00 0x4114000 0x00 0x100>;
1172 			reg = <0x00 0x6400000 0x00 0x10000>,
1173 			      <0x00 0x6410000 0x00 0x10000>,
1174 			      <0x00 0x6420000 0x00 0x10000>;
1176 			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
1178 				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
1189 		reg = <0x0 0x2000000 0x0 0x100>;
1192 		#size-cells = <0>;
1194 		clocks = <&k3_clks 187 0>;
1200 		reg = <0x0 0x2010000 0x0 0x100>;
1203 		#size-cells = <0>;
1205 		clocks = <&k3_clks 188 0>;
1211 		reg = <0x0 0x2020000 0x0 0x100>;
1214 		#size-cells = <0>;
1216 		clocks = <&k3_clks 189 0>;
1222 		reg = <0x0 0x2030000 0x0 0x100>;
1225 		#size-cells = <0>;
1227 		clocks = <&k3_clks 190 0>;
1233 		reg = <0x0 0x2040000 0x0 0x100>;
1236 		#size-cells = <0>;
1238 		clocks = <&k3_clks 191 0>;
1244 		reg = <0x0 0x2050000 0x0 0x100>;
1247 		#size-cells = <0>;
1249 		clocks = <&k3_clks 192 0>;
1255 		reg = <0x0 0x2060000 0x0 0x100>;
1258 		#size-cells = <0>;
1260 		clocks = <&k3_clks 193 0>;
1266 		reg = <0x0 0x4e80000 0x0 0x100>;
1277 			reg = <0x0 0x4e84000 0x0 0x10000>;
1280 			clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
1289 			<0x00 0x04a00000 0x00 0x10000>, /* common_m */
1290 			<0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1291 			<0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1292 			<0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1294 			<0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1295 			<0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1296 			<0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1297 			<0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1299 			<0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1300 			<0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1301 			<0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1302 			<0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1304 			<0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1305 			<0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1306 			<0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1307 			<0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1308 			<0x00 0x04af0000 0x00 0x10000>; /* wb */
1317 		clocks =	<&k3_clks 152 0>,
1339 			#size-cells = <0>;
1345 		reg = <0x0 0x02b00000 0x0 0x2000>,
1346 			<0x0 0x02b08000 0x0 0x1000>;
1352 		dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
1364 		reg = <0x0 0x02b10000 0x0 0x2000>,
1365 			<0x0 0x02b18000 0x0 0x1000>;
1371 		dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
1383 		reg = <0x0 0x02b20000 0x0 0x2000>,
1384 			<0x0 0x02b28000 0x0 0x1000>;
1390 		dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
1402 		reg = <0x0 0x02b30000 0x0 0x2000>,
1403 			<0x0 0x02b38000 0x0 0x1000>;
1409 		dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
1421 		reg = <0x0 0x02b40000 0x0 0x2000>,
1422 			<0x0 0x02b48000 0x0 0x1000>;
1428 		dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
1440 		reg = <0x0 0x02b50000 0x0 0x2000>,
1441 			<0x0 0x02b58000 0x0 0x1000>;
1447 		dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
1459 		reg = <0x0 0x02b60000 0x0 0x2000>,
1460 			<0x0 0x02b68000 0x0 0x1000>;
1466 		dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
1478 		reg = <0x0 0x02b70000 0x0 0x2000>,
1479 			<0x0 0x02b78000 0x0 0x1000>;
1485 		dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
1497 		reg = <0x0 0x02b80000 0x0 0x2000>,
1498 			<0x0 0x02b88000 0x0 0x1000>;
1504 		dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
1516 		reg = <0x0 0x02b90000 0x0 0x2000>,
1517 			<0x0 0x02b98000 0x0 0x1000>;
1523 		dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
1535 		reg = <0x0 0x02ba0000 0x0 0x2000>,
1536 			<0x0 0x02ba8000 0x0 0x1000>;
1542 		dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
1554 		reg = <0x0 0x02bb0000 0x0 0x2000>,
1555 			<0x0 0x02bb8000 0x0 0x1000>;
1561 		dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
1573 		reg = <0x0 0x2200000 0x0 0x100>;
1582 		reg = <0x0 0x2210000 0x0 0x100>;
1591 		reg = <0x4d 0x80800000 0x00 0x00048000>,
1592 		      <0x4d 0x80e00000 0x00 0x00008000>,
1593 		      <0x4d 0x80f00000 0x00 0x00008000>;
1597 		ti,sci-proc-ids = <0x03 0xff>;
1604 		reg = <0x4d 0x81800000 0x00 0x00048000>,
1605 		      <0x4d 0x81e00000 0x00 0x00008000>,
1606 		      <0x4d 0x81f00000 0x00 0x00008000>;
1610 		ti,sci-proc-ids = <0x04 0xff>;
1617 		reg = <0x00 0x64800000 0x00 0x00080000>,
1618 		      <0x00 0x64e00000 0x00 0x0000c000>;
1622 		ti,sci-proc-ids = <0x30 0xff>;