Lines Matching +full:0 +full:x34000000
11 reg = <0x00 0x70000000 0x00 0x100000>;
14 ranges = <0x00 0x00 0x70000000 0x100000>;
16 atf-sram@0 {
17 reg = <0x00 0x20000>;
23 reg = <0x00 0x00100000 0x00 0x1c000>;
26 ranges = <0x00 0x00 0x00100000 0x1c000>;
31 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
32 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
38 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
49 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
50 <0x00 0x01900000 0x00 0x100000>, /* GICR */
51 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
52 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
53 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
60 reg = <0x00 0x01820000 0x00 0x10000>;
61 socionext,synquacer-pre-its = <0x1000000 0x400000>;
82 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
95 ti,interrupt-ranges = <0 64 64>,
102 reg = <0x00 0x33d00000 0x00 0x100000>;
104 #interrupt-cells = <0>;
109 ti,interrupt-ranges = <0 0 256>;
116 reg = <0x00 0x32c00000 0x00 0x100000>,
117 <0x00 0x32400000 0x00 0x100000>,
118 <0x00 0x32800000 0x00 0x100000>;
125 reg = <0x00 0x3c000000 0x00 0x400000>,
126 <0x00 0x38000000 0x00 0x400000>,
127 <0x00 0x31120000 0x00 0x100>,
128 <0x00 0x33000000 0x00 0x40000>;
131 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
139 reg = <0x00 0x31150000 0x00 0x100>,
140 <0x00 0x34000000 0x00 0x100000>,
141 <0x00 0x35000000 0x00 0x100000>;
150 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
151 <0x0f>, /* TX_HCHAN */
152 <0x10>; /* TX_UHCHAN */
153 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
154 <0x0b>, /* RX_HCHAN */
155 <0x0c>; /* RX_UHCHAN */
156 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
161 reg = <0x00 0x310d0000 0x00 0x400>;
174 /* Proxy 0 addressing */
175 reg = <0x00 0x11c000 0x00 0x2b4>;
178 pinctrl-single,function-mask = <0xffffffff>;
183 reg = <0x00 0x02800000 0x00 0x100>;
196 reg = <0x00 0x02810000 0x00 0x100>;
209 reg = <0x00 0x02820000 0x00 0x100>;
222 reg = <0x00 0x02830000 0x00 0x100>;
235 reg = <0x00 0x02840000 0x00 0x100>;
248 reg = <0x00 0x02850000 0x00 0x100>;
261 reg = <0x00 0x02860000 0x00 0x100>;
274 reg = <0x00 0x02870000 0x00 0x100>;
287 reg = <0x00 0x02880000 0x00 0x100>;
300 reg = <0x00 0x02890000 0x00 0x100>;
313 reg = <0x00 0x2000000 0x00 0x100>;
316 #size-cells = <0>;
324 reg = <0x00 0x2010000 0x00 0x100>;
327 #size-cells = <0>;
335 reg = <0x00 0x2020000 0x00 0x100>;
338 #size-cells = <0>;
346 reg = <0x00 0x2030000 0x00 0x100>;
349 #size-cells = <0>;
357 reg = <0x00 0x2040000 0x00 0x100>;
360 #size-cells = <0>;
368 reg = <0x00 0x2050000 0x00 0x100>;
371 #size-cells = <0>;
379 reg = <0x00 0x2060000 0x00 0x100>;
382 #size-cells = <0>;
390 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>;
394 clocks = <&k3_clks 91 3>, <&k3_clks 91 0>;
395 ti,otap-del-sel-legacy = <0x0>;
396 ti,otap-del-sel-mmc-hs = <0x0>;
397 ti,otap-del-sel-ddr52 = <0x6>;
398 ti,otap-del-sel-hs200 = <0x8>;
399 ti,otap-del-sel-hs400 = <0x0>;
400 ti,strobe-sel = <0x77>;
401 ti,trm-icp = <0x8>;
409 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>;
414 ti,otap-del-sel-legacy = <0x0>;
415 ti,otap-del-sel-sd-hs = <0x0>;
416 ti,otap-del-sel-sdr12 = <0xf>;
417 ti,otap-del-sel-sdr25 = <0xf>;
418 ti,otap-del-sel-sdr50 = <0xc>;
419 ti,otap-del-sel-sdr104 = <0x5>;
420 ti,otap-del-sel-ddr50 = <0xc>;
427 reg = <0x00 0x4104000 0x00 0x100>;
440 reg = <0x00 0x6000000 0x00 0x10000>,
441 <0x00 0x6010000 0x00 0x10000>,
442 <0x00 0x6020000 0x00 0x10000>;
444 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
446 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */