Lines Matching +full:0 +full:x34000000
12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
41 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
50 reg = <0x00 0x01820000 0x00 0x10000>;
51 socionext,synquacer-pre-its = <0x1000000 0x400000>;
59 reg = <0x0 0x900000 0x0 0x2000>;
69 mux-controls = <&serdes_mux 0>;
74 reg = <0x0 0x910000 0x0 0x2000>;
89 reg = <0x00 0x02800000 0x00 0x100>;
100 reg = <0x00 0x02810000 0x00 0x100>;
110 reg = <0x00 0x02820000 0x00 0x100>;
120 reg = <0x0 0x4e00000 0x0 0x1200>;
124 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
127 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
128 <&main_udmap 0x4001>;
134 reg = <0x0 0x4e10000 0x0 0x7d>;
142 reg = <0x0 0x11c000 0x0 0x2e4>;
145 pinctrl-single,function-mask = <0xffffffff>;
150 reg = <0x0 0x11c2e8 0x0 0x24>;
153 pinctrl-single,function-mask = <0xffffffff>;
158 reg = <0x0 0x2000000 0x0 0x100>;
161 #size-cells = <0>;
169 reg = <0x0 0x2010000 0x0 0x100>;
172 #size-cells = <0>;
180 reg = <0x0 0x2020000 0x0 0x100>;
183 #size-cells = <0>;
191 reg = <0x0 0x2030000 0x0 0x100>;
194 #size-cells = <0>;
203 reg = <0x0 0x03100000 0x0 0x60>;
205 clocks = <&k3_clks 39 0>;
211 reg = <0x0 0x2100000 0x0 0x400>;
216 #size-cells = <0>;
217 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
223 reg = <0x0 0x2110000 0x0 0x400>;
228 #size-cells = <0>;
235 reg = <0x0 0x2120000 0x0 0x400>;
240 #size-cells = <0>;
245 reg = <0x0 0x2130000 0x0 0x400>;
250 #size-cells = <0>;
255 reg = <0x0 0x2140000 0x0 0x400>;
260 #size-cells = <0>;
265 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
267 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
272 ti,otap-del-sel-legacy = <0x0>;
273 ti,otap-del-sel-mmc-hs = <0x0>;
274 ti,otap-del-sel-sd-hs = <0x0>;
275 ti,otap-del-sel-sdr12 = <0x0>;
276 ti,otap-del-sel-sdr25 = <0x0>;
277 ti,otap-del-sel-sdr50 = <0x8>;
278 ti,otap-del-sel-sdr104 = <0x7>;
279 ti,otap-del-sel-ddr50 = <0x5>;
280 ti,otap-del-sel-ddr52 = <0x5>;
281 ti,otap-del-sel-hs200 = <0x5>;
282 ti,otap-del-sel-hs400 = <0x0>;
283 ti,trm-icp = <0x8>;
289 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
291 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
294 ti,otap-del-sel-legacy = <0x0>;
295 ti,otap-del-sel-mmc-hs = <0x0>;
296 ti,otap-del-sel-sd-hs = <0x0>;
297 ti,otap-del-sel-sdr12 = <0x0>;
298 ti,otap-del-sel-sdr25 = <0x0>;
299 ti,otap-del-sel-sdr50 = <0x8>;
300 ti,otap-del-sel-sdr104 = <0x7>;
301 ti,otap-del-sel-ddr50 = <0x4>;
302 ti,otap-del-sel-ddr52 = <0x4>;
303 ti,otap-del-sel-hs200 = <0x7>;
304 ti,clkbuf-sel = <0x7>;
305 ti,otap-del-sel = <0x2>;
306 ti,trm-icp = <0x8>;
313 reg = <0 0x00100000 0 0x1c000>;
316 ranges = <0x0 0x0 0x00100000 0x1c000>;
320 reg = <0x00004060 0x4>;
325 reg = <0x00004070 0x4>;
330 reg = <0x00000210 0x4>;
335 reg = <0x00004080 0x4>;
340 reg = <0x00004090 0x4>;
346 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
347 <0x4090 0x3>; /* SERDES1 lane select */
352 reg = <0x0000041e0 0x14>;
357 reg = <0x4140 0x18>;
364 reg = <0x0 0x4000000 0x0 0x4000>;
367 ranges = <0x0 0x0 0x4000000 0x20000>;
378 reg = <0x10000 0x10000>;
395 reg = <0x0 0x4100000 0x0 0x54>;
396 syscon-phy-power = <&scm_conf 0x4000>;
397 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
399 #phy-cells = <0>;
404 reg = <0x0 0x4020000 0x0 0x4000>;
407 ranges = <0x0 0x0 0x4020000 0x20000>;
417 reg = <0x10000 0x10000>;
433 reg = <0x0 0x4110000 0x0 0x54>;
434 syscon-phy-power = <&scm_conf 0x4020>;
435 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
437 #phy-cells = <0>;
448 ti,interrupt-ranges = <0 392 32>;
469 ti,interrupt-ranges = <0 64 64>,
475 reg = <0x0 0x33d00000 0x0 0x100000>;
481 ti,interrupt-ranges = <0 0 256>;
488 reg = <0x00 0x32c00000 0x00 0x100000>,
489 <0x00 0x32400000 0x00 0x100000>,
490 <0x00 0x32800000 0x00 0x100000>;
497 reg = <0x00 0x30e00000 0x00 0x1000>;
503 reg = <0x00 0x31f80000 0x00 0x200>;
512 reg = <0x00 0x31f81000 0x00 0x200>;
521 reg = <0x00 0x31f82000 0x00 0x200>;
530 reg = <0x00 0x31f83000 0x00 0x200>;
539 reg = <0x00 0x31f84000 0x00 0x200>;
548 reg = <0x00 0x31f85000 0x00 0x200>;
557 reg = <0x00 0x31f86000 0x00 0x200>;
566 reg = <0x00 0x31f87000 0x00 0x200>;
575 reg = <0x00 0x31f88000 0x00 0x200>;
584 reg = <0x00 0x31f89000 0x00 0x200>;
593 reg = <0x00 0x31f8a000 0x00 0x200>;
602 reg = <0x00 0x31f8b000 0x00 0x200>;
611 reg = <0x0 0x3c000000 0x0 0x400000>,
612 <0x0 0x38000000 0x0 0x400000>,
613 <0x0 0x31120000 0x0 0x100>,
614 <0x0 0x33000000 0x0 0x40000>;
617 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
626 reg = <0x0 0x31150000 0x0 0x100>,
627 <0x0 0x34000000 0x0 0x100000>,
628 <0x0 0x35000000 0x0 0x100000>;
637 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
638 <0xd>; /* TX_CHAN */
639 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
640 <0xa>; /* RX_CHAN */
641 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
646 reg = <0x0 0x310d0000 0x0 0x400>;
656 #clock-cells = <0>;
669 reg = <0x0 0x600000 0x0 0x100>;
677 ti,davinci-gpio-unbanked = <0>;
678 clocks = <&k3_clks 57 0>;
684 reg = <0x0 0x601000 0x0 0x100>;
692 ti,davinci-gpio-unbanked = <0>;
693 clocks = <&k3_clks 58 0>;
699 …reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0…
704 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
705 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
708 bus-range = <0x0 0xff>;
713 msi-map = <0x0 &gic_its 0x0 0x10000>;
718 …reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x…
731 …reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0…
736 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000
737 0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
740 bus-range = <0x0 0xff>;
745 msi-map = <0x0 &gic_its 0x10000 0x10000>;
750 …reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x…
763 reg = <0x0 0x02b00000 0x0 0x2000>,
764 <0x0 0x02b08000 0x0 0x1000>;
770 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
773 clocks = <&k3_clks 104 0>;
782 reg = <0x0 0x02b10000 0x0 0x2000>,
783 <0x0 0x02b18000 0x0 0x1000>;
789 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
792 clocks = <&k3_clks 105 0>;
801 reg = <0x0 0x02b20000 0x0 0x2000>,
802 <0x0 0x02b28000 0x0 0x1000>;
808 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
811 clocks = <&k3_clks 106 0>;
820 reg = <0x0 0x06f03000 0x0 0x400>,
821 <0x0 0x06f03800 0x0 0x40>;
825 ti,camerrx-control = <&scm_conf 0x40c0>;
827 clocks = <&k3_clks 2 0>;
832 #size-cells = <0>;
834 csi2_0: port@0 {
835 reg = <0>;
842 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
843 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
844 <0x0 0x04a06000 0x0 0x1000>, /* vid */
845 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
846 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
847 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
848 <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
877 #size-cells = <0>;
884 reg = <0x0 0x3000000 0x0 0x100>;
886 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
893 reg = <0x0 0x3010000 0x0 0x100>;
895 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
902 reg = <0x0 0x3020000 0x0 0x100>;
904 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
911 reg = <0x0 0x3030000 0x0 0x100>;
913 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
920 reg = <0x0 0x3040000 0x0 0x100>;
922 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
929 reg = <0x0 0x3050000 0x0 0x100>;
931 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;