Lines Matching full:cru
6 #include <dt-bindings/clock/rk3588-cru.h>
112 clocks = <&cru HCLK_VO1USB_TOP_ROOT>;
121 clocks = <&cru ACLK_VDPU_ROOT>;
130 clocks = <&cru HCLK_VOP_ROOT>;
139 clocks = <&cru HCLK_VO1USB_TOP_ROOT>;
148 clocks = <&cru ACLK_NVM_ROOT>;
157 clocks = <&cru ACLK_VO1USB_TOP_ROOT>;
166 clocks = <&cru HCLK_VI_ROOT>;
175 clocks = <&cru ACLK_VI_ROOT>;
184 clocks = <&cru ACLK_VDPU_ROOT>;
193 clocks = <&cru HCLK_VDPU_ROOT>;
202 clocks = <&cru ACLK_VDPU_ROOT>;
211 clocks = <&cru HCLK_VDPU_ROOT>;
220 clocks = <&cru ACLK_VDPU_ROOT>;
229 clocks = <&cru ACLK_RKVENC0>;
238 clocks = <&cru HCLK_RKVENC0>;
247 clocks = <&cru ACLK_VOP_LOW_ROOT>;
256 clocks = <&cru ACLK_VO1USB_TOP_ROOT>;
265 clocks = <&cru HCLK_VDPU_ROOT>;
274 clocks = <&cru ACLK_VDPU_ROOT>;
335 clocks = <&cru I2S0_8CH_MCLKOUT>;
345 clocks = <&cru I2S1_8CH_MCLKOUT>;
355 clocks = <&cru I2S1_8CH_MCLKOUT>;
364 clocks = <&cru I2S2_2CH_MCLKOUT>;
374 clocks = <&cru I2S3_2CH_MCLKOUT>;
2307 clocks = <&scmi_clk SCMI_CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
2308 <&cru CLK_GPU_STACKS>, <&cru CLK_GPU>;
2357 clocks = <&cru CLK_GPU>;
2554 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
2555 <&cru ACLK_USB3OTG0>;
2567 resets = <&cru SRST_A_USB3OTG0>;
2589 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&u2phy2>;
2602 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&u2phy2>;
2614 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&u2phy3>;
2627 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&u2phy3>;
2661 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
2662 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
2663 <&cru PCLK_PHP_ROOT>, <&cru CLK_PIPEPHY2_PIPE_U3_G>;
2674 resets = <&cru SRST_A_USB3OTG2>;
2837 resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
2839 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
2864 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
2866 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
2890 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
2892 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
2925 cru: clock-controller@fd7c0000 { label
2926 compatible = "rockchip,rk3588-cru";
2933 <&cru PLL_PPLL>, <&cru PLL_AUPLL>,
2934 <&cru PLL_NPLL>, <&cru PLL_GPLL>,
2935 <&cru ACLK_CENTER_ROOT>,
2936 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
2937 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
2938 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
2939 <&cru HCLK_PMU_CM0_ROOT>,
2940 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
2941 <&cru CLK_GPU>, <&cru CLK_SPDIF2_DP0>,
2942 <&cru CLK_SPDIF5_DP1>, <&cru CLK_HDMIRX_AUD>,
2943 <&cru DCLK_DECOM>;
2961 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
2975 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
2992 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
3004 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
3016 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
3029 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
3055 clocks = <&cru HCLK_NPU_ROOT>,
3056 <&cru PCLK_NPU_ROOT>,
3057 <&cru CLK_NPU_DSU0>,
3058 <&cru HCLK_NPU_CM0_ROOT>;
3065 clocks = <&cru HCLK_NPU_ROOT>,
3066 <&cru PCLK_NPU_ROOT>,
3067 <&cru CLK_NPU_DSU0>;
3072 clocks = <&cru HCLK_NPU_ROOT>,
3073 <&cru PCLK_NPU_ROOT>,
3074 <&cru CLK_NPU_DSU0>;
3082 clocks = <&cru CLK_GPU>,
3083 <&cru CLK_GPU_COREGROUP>,
3084 <&cru CLK_GPU_STACKS>;
3098 clocks = <&cru HCLK_RKVDEC0>,
3099 <&cru HCLK_VDPU_ROOT>,
3100 <&cru ACLK_VDPU_ROOT>,
3101 <&cru ACLK_RKVDEC0>,
3102 <&cru ACLK_RKVDEC_CCU>;
3107 clocks = <&cru HCLK_RKVDEC1>,
3108 <&cru HCLK_VDPU_ROOT>,
3109 <&cru ACLK_VDPU_ROOT>,
3110 <&cru ACLK_RKVDEC1>;
3117 clocks = <&cru HCLK_RKVENC0>,
3118 <&cru ACLK_RKVENC0>;
3125 clocks = <&cru HCLK_RKVENC1>,
3126 <&cru HCLK_RKVENC0>,
3127 <&cru ACLK_RKVENC0>,
3128 <&cru ACLK_RKVENC1>;
3140 clocks = <&cru HCLK_VDPU_ROOT>,
3141 <&cru ACLK_VDPU_LOW_ROOT>,
3142 <&cru ACLK_VDPU_ROOT>,
3143 <&cru ACLK_JPEG_DECODER_ROOT>,
3144 <&cru ACLK_IEP2P0>,
3145 <&cru HCLK_IEP2P0>,
3146 <&cru ACLK_JPEG_ENCODER0>,
3147 <&cru HCLK_JPEG_ENCODER0>,
3148 <&cru ACLK_JPEG_ENCODER1>,
3149 <&cru HCLK_JPEG_ENCODER1>,
3150 <&cru ACLK_JPEG_ENCODER2>,
3151 <&cru HCLK_JPEG_ENCODER2>,
3152 <&cru ACLK_JPEG_ENCODER3>,
3153 <&cru HCLK_JPEG_ENCODER3>,
3154 <&cru ACLK_JPEG_DECODER>,
3155 <&cru HCLK_JPEG_DECODER>,
3156 <&cru ACLK_RGA2>,
3157 <&cru HCLK_RGA2>;
3169 clocks = <&cru PCLK_AV1>,
3170 <&cru ACLK_AV1>,
3171 <&cru HCLK_VDPU_ROOT>;
3176 clocks = <&cru HCLK_RKVDEC0>,
3177 <&cru HCLK_VDPU_ROOT>,
3178 <&cru ACLK_VDPU_ROOT>,
3179 <&cru ACLK_RKVDEC0>;
3184 clocks = <&cru HCLK_RKVDEC1>,
3185 <&cru HCLK_VDPU_ROOT>,
3186 <&cru ACLK_VDPU_ROOT>;
3191 clocks = <&cru ACLK_RGA3_0>,
3192 <&cru HCLK_RGA3_0>;
3200 clocks = <&cru PCLK_VOP_ROOT>,
3201 <&cru HCLK_VOP_ROOT>,
3202 <&cru ACLK_VOP>;
3208 clocks = <&cru PCLK_VO0_ROOT>,
3209 <&cru PCLK_VO0_S_ROOT>,
3210 <&cru HCLK_VO0_S_ROOT>,
3211 <&cru ACLK_VO0_ROOT>,
3212 <&cru HCLK_HDCP0>,
3213 <&cru ACLK_HDCP0>,
3214 <&cru HCLK_VOP_ROOT>;
3220 clocks = <&cru PCLK_VO1_ROOT>,
3221 <&cru PCLK_VO1_S_ROOT>,
3222 <&cru HCLK_VO1_S_ROOT>,
3223 <&cru HCLK_HDCP1>,
3224 <&cru ACLK_HDCP1>,
3225 <&cru ACLK_HDMIRX_ROOT>,
3226 <&cru HCLK_VO1USB_TOP_ROOT>;
3234 clocks = <&cru HCLK_VI_ROOT>,
3235 <&cru PCLK_VI_ROOT>,
3236 <&cru HCLK_ISP0>,
3237 <&cru ACLK_ISP0>,
3238 <&cru HCLK_VICAP>,
3239 <&cru ACLK_VICAP>;
3247 clocks = <&cru HCLK_ISP1>,
3248 <&cru ACLK_ISP1>,
3249 <&cru HCLK_VI_ROOT>,
3250 <&cru PCLK_VI_ROOT>;
3256 clocks = <&cru HCLK_FISHEYE0>,
3257 <&cru ACLK_FISHEYE0>,
3258 <&cru HCLK_FISHEYE1>,
3259 <&cru ACLK_FISHEYE1>,
3260 <&cru PCLK_VI_ROOT>;
3267 clocks = <&cru HCLK_RGA3_1>,
3268 <&cru ACLK_RGA3_1>;
3273 clocks = <&cru PCLK_PHP_ROOT>,
3274 <&cru ACLK_USB_ROOT>,
3275 <&cru HCLK_USB_ROOT>,
3276 <&cru HCLK_HOST0>,
3277 <&cru HCLK_HOST_ARB0>,
3278 <&cru HCLK_HOST1>,
3279 <&cru HCLK_HOST_ARB1>;
3287 clocks = <&cru PCLK_PHP_ROOT>,
3288 <&cru ACLK_PCIE_ROOT>,
3289 <&cru ACLK_PHP_ROOT>;
3293 clocks = <&cru PCLK_PHP_ROOT>,
3294 <&cru ACLK_PCIE_ROOT>,
3295 <&cru ACLK_PHP_ROOT>;
3299 clocks = <&cru HCLK_SDIO>,
3300 <&cru HCLK_NVM_ROOT>;
3305 clocks = <&cru HCLK_AUDIO_ROOT>,
3306 <&cru PCLK_AUDIO_ROOT>;
3322 clocks = <&cru CLK_BIGCORE0_PVTM>, <&cru PCLK_BIGCORE0_PVTM>;
3334 clocks = <&cru CLK_BIGCORE1_PVTM>, <&cru PCLK_BIGCORE1_PVTM>;
3346 clocks = <&cru CLK_LITCORE_PVTM>, <&cru PCLK_LITCORE_PVTM>;
3358 clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>;
3360 resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>;
3372 clocks = <&cru CLK_GPU_PVTM>;
3374 resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>;
3388 clocks = <&scmi_clk SCMI_CLK_NPU>, <&cru ACLK_NPU0>,
3389 <&cru ACLK_NPU1>, <&cru ACLK_NPU2>,
3390 <&cru HCLK_NPU0>, <&cru HCLK_NPU1>,
3391 <&cru HCLK_NPU2>, <&cru PCLK_NPU_ROOT>;
3398 resets = <&cru SRST_A_RKNN0>, <&cru SRST_A_RKNN1>, <&cru SRST_A_RKNN2>,
3399 <&cru SRST_H_RKNN0>, <&cru SRST_H_RKNN1>, <&cru SRST_H_RKNN2>;
3444 clocks = <&cru PCLK_NPU_GRF>;
3652 clocks = <&cru ACLK_NPU0>, <&cru ACLK_NPU1>, <&cru ACLK_NPU2>,
3653 <&cru HCLK_NPU0>, <&cru HCLK_NPU1>, <&cru HCLK_NPU2>;
3665 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
3668 assigned-clocks = <&cru ACLK_VPU>;
3670 resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>;
3687 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
3690 assigned-clocks = <&cru ACLK_VPU>;
3692 resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>;
3709 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
3721 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
3724 assigned-clocks = <&cru ACLK_VPU>;
3726 resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>;
3743 clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>, <&cru CLK_RGA3_0_CORE>;
3755 clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>;
3767 clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>, <&cru CLK_RGA3_1_CORE>;
3779 clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>;
3791 clocks = <&cru ACLK_RGA2>, <&cru HCLK_RGA2>, <&cru CLK_RGA2_CORE>;
3802 clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>;
3805 assigned-clocks = <&cru ACLK_JPEG_DECODER>;
3807 resets = <&cru SRST_A_JPEG_DECODER>, <&cru SRST_H_JPEG_DECODER>;
3822 clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>;
3834 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
3837 assigned-clocks = <&cru ACLK_JPEG_ENCODER0>;
3839 resets = <&cru SRST_A_JPEG_ENCODER0>, <&cru SRST_H_JPEG_ENCODER0>;
3856 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
3868 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
3871 assigned-clocks = <&cru ACLK_JPEG_ENCODER1>;
3873 resets = <&cru SRST_A_JPEG_ENCODER1>, <&cru SRST_H_JPEG_ENCODER1>;
3890 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
3902 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
3905 assigned-clocks = <&cru ACLK_JPEG_ENCODER2>;
3907 resets = <&cru SRST_A_JPEG_ENCODER2>, <&cru SRST_H_JPEG_ENCODER2>;
3924 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
3936 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
3939 assigned-clocks = <&cru ACLK_JPEG_ENCODER3>;
3941 resets = <&cru SRST_A_JPEG_ENCODER3>, <&cru SRST_H_JPEG_ENCODER3>;
3958 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
3970 clocks = <&cru ACLK_IEP2P0>, <&cru HCLK_IEP2P0>, <&cru CLK_IEP2P0_CORE>;
3973 assigned-clocks = <&cru ACLK_IEP2P0>;
3975 resets = <&cru SRST_A_IEP2P0>, <&cru SRST_H_IEP2P0>, <&cru SRST_IEP2P0_CORE>;
3991 clocks = <&cru ACLK_IEP2P0>, <&cru HCLK_IEP2P0>;
4003 clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>, <&cru CLK_RKVENC0_CORE>;
4006 assigned-clocks = <&cru ACLK_RKVENC0>, <&cru CLK_RKVENC0_CORE>;
4008 resets = <&cru SRST_A_RKVENC0>, <&cru SRST_H_RKVENC0>, <&cru SRST_RKVENC0_CORE>;
4027 clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>;
4042 clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>, <&cru CLK_RKVENC1_CORE>;
4045 assigned-clocks = <&cru ACLK_RKVENC1>, <&cru CLK_RKVENC1_CORE>;
4047 resets = <&cru SRST_A_RKVENC1>, <&cru SRST_H_RKVENC1>, <&cru SRST_RKVENC1_CORE>;
4066 clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>;
4112 clocks = <&cru ACLK_RKVDEC_CCU>;
4114 assigned-clocks = <&cru ACLK_RKVDEC_CCU>;
4116 resets = <&cru SRST_A_RKVDEC_CCU>;
4131 clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>,
4132 <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>;
4137 assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>,
4138 <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>;
4141 resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CORE>,
4142 <&cru SRST_RKVDEC0_CA>, <&cru SRST_RKVDEC0_HEVC_CA>;
4168 clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>;
4185 clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>,
4186 <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>;
4191 assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>,
4192 <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>;
4195 resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CORE>,
4196 <&cru SRST_RKVDEC1_CA>, <&cru SRST_RKVDEC1_HEVC_CA>;
4222 clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>;
4241 clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
4244 assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
4246 resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>;
4260 clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
4275 clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>,
4276 <&cru CLK_ISP0_CORE>, <&cru CLK_ISP0_CORE_MARVIN>,
4277 <&cru CLK_ISP0_CORE_VICAP>, <&cru ACLK_ISP1>,
4278 <&cru HCLK_ISP1>, <&cru CLK_ISP1_CORE>,
4279 <&cru CLK_ISP1_CORE_MARVIN>, <&cru CLK_ISP1_CORE_VICAP>;
4296 clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>,
4297 <&cru CLK_ISP0_CORE>, <&cru CLK_ISP0_CORE_MARVIN>,
4298 <&cru CLK_ISP0_CORE_VICAP>;
4312 clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>,
4313 <&cru ACLK_ISP1>, <&cru HCLK_ISP1>;
4326 clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>;
4341 clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>,
4342 <&cru CLK_ISP1_CORE>, <&cru CLK_ISP1_CORE_MARVIN>,
4343 <&cru CLK_ISP1_CORE_VICAP>;
4356 clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>;
4369 clocks = <&cru ACLK_FISHEYE0>, <&cru HCLK_FISHEYE0>,
4370 <&cru CLK_FISHEYE0_CORE>;
4372 assigned-clocks = <&cru HCLK_FISHEYE0>;
4384 clocks = <&cru ACLK_FISHEYE0>, <&cru HCLK_FISHEYE0>, <&cru CLK_FISHEYE0_CORE>;
4397 clocks = <&cru ACLK_FISHEYE1>, <&cru HCLK_FISHEYE1>,
4398 <&cru CLK_FISHEYE1_CORE>;
4400 assigned-clocks = <&cru HCLK_FISHEYE1>;
4412 clocks = <&cru ACLK_FISHEYE1>, <&cru HCLK_FISHEYE1>, <&cru CLK_FISHEYE1_CORE>;
4426 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, <&cru DCLK_VICAP>,
4427 <&cru ICLK_CSIHOST0>, <&cru ICLK_CSIHOST1>;
4430 resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, <&cru SRST_D_VICAP>,
4431 <&cru SRST_CSIHOST0_VICAP>, <&cru SRST_CSIHOST1_VICAP>,
4432 <&cru SRST_CSIHOST2_VICAP>, <&cru SRST_CSIHOST3_VICAP>,
4433 <&cru SRST_CSIHOST4_VICAP>, <&cru SRST_CSIHOST5_VICAP>;
4437 assigned-clocks = <&cru DCLK_VICAP>;
4457 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>;
4472 clocks = <&cru PCLK_CSI_HOST_0>;
4474 resets = <&cru SRST_P_CSI_HOST_0>;
4486 clocks = <&cru PCLK_CSI_HOST_1>;
4488 resets = <&cru SRST_P_CSI_HOST_1>;
4500 clocks = <&cru PCLK_CSI_HOST_2>;
4502 resets = <&cru SRST_P_CSI_HOST_2>;
4514 clocks = <&cru PCLK_CSI_HOST_3>;
4516 resets = <&cru SRST_P_CSI_HOST_3>;
4528 clocks = <&cru PCLK_CSI_HOST_4>;
4530 resets = <&cru SRST_P_CSI_HOST_4>;
4542 clocks = <&cru PCLK_CSI_HOST_5>;
4544 resets = <&cru SRST_P_CSI_HOST_5>;
4554 clocks = <&cru ACLK_VOP>,
4555 <&cru HCLK_VOP>,
4556 <&cru DCLK_VOP0>,
4557 <&cru DCLK_VOP1>,
4558 <&cru DCLK_VOP2>,
4559 <&cru DCLK_VOP3>,
4560 <&cru PCLK_VOP_ROOT>,
4561 <&cru DCLK_VOP0_SRC>,
4562 <&cru DCLK_VOP1_SRC>,
4563 <&cru DCLK_VOP2_SRC>;
4574 assigned-clocks = <&cru ACLK_VOP>;
4576 resets = <&cru SRST_A_VOP>,
4577 <&cru SRST_H_VOP>,
4578 <&cru SRST_D_VOP0>,
4579 <&cru SRST_D_VOP1>,
4580 <&cru SRST_D_VOP2>,
4581 <&cru SRST_D_VOP3>;
4648 assigned-clocks = <&cru DCLK_VOP2_SRC>;
4649 assigned-clock-parents = <&cru PLL_V0PLL>;
4705 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
4720 clocks = <&cru MCLK_SPDIF2>, <&cru HCLK_SPDIF2_DP0>;
4721 assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>;
4722 assigned-clock-parents = <&cru PLL_AUPLL>;
4732 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
4734 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
4735 assigned-clock-parents = <&cru PLL_AUPLL>;
4739 resets = <&cru SRST_M_I2S4_8CH_TX>;
4753 clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>;
4754 assigned-clocks = <&cru CLK_SPDIF3_SRC>;
4755 assigned-clock-parents = <&cru PLL_AUPLL>;
4765 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
4767 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
4768 assigned-clock-parents = <&cru PLL_GPLL>;
4772 resets = <&cru SRST_M_I2S5_8CH_TX>;
4785 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
4787 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
4788 assigned-clock-parents = <&cru PLL_AUPLL>;
4792 resets = <&cru SRST_M_I2S9_8CH_RX>;
4803 clocks = <&cru MCLK_SPDIFRX0>, <&cru HCLK_SPDIFRX0>;
4805 assigned-clocks = <&cru MCLK_SPDIFRX0>;
4806 assigned-clock-parents = <&cru PLL_AUPLL>;
4810 resets = <&cru SRST_M_SPDIFRX0>;
4820 clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>;
4822 resets = <&cru SRST_P_DSIHOST0>;
4860 clocks = <&cru PCLK_DSIHOST1>, <&cru CLK_DSIHOST1>;
4862 resets = <&cru SRST_P_DSIHOST1>;
4900 clocks = <&cru ACLK_HDCP0>, <&cru PCLK_HDCP0>,
4901 <&cru HCLK_HDCP0>, <&cru HCLK_HDCP_KEY0>,
4902 <&cru ACLK_TRNG0>, <&cru PCLK_TRNG0>;
4904 resets = <&cru SRST_HDCP0>, <&cru SRST_H_HDCP0>,
4905 <&cru SRST_A_HDCP0>, <&cru SRST_H_HDCP_KEY0>,
4906 <&cru SRST_P_TRNG0>;
4917 clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>,
4918 <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_SPDIF2_DP0>,
4919 <&hclk_vo0>, <&cru CLK_DP0>;
4921 assigned-clocks = <&cru CLK_AUX16M_0>;
4923 resets = <&cru SRST_DP0>;
4969 clocks = <&cru ACLK_HDCP1>, <&cru PCLK_HDCP1>,
4970 <&cru HCLK_HDCP1>, <&cru HCLK_HDCP_KEY1>,
4971 <&cru ACLK_TRNG1>, <&cru PCLK_TRNG1>;
4973 resets = <&cru SRST_HDCP1>, <&cru SRST_H_HDCP1>,
4974 <&cru SRST_A_HDCP1>, <&cru SRST_H_HDCP_KEY1>,
4975 <&cru SRST_P_TRNG1>;
4990 clocks = <&cru PCLK_HDMITX0>,
4991 <&cru CLK_HDMIHDP0>,
4992 <&cru CLK_HDMITX0_EARC>,
4993 <&cru CLK_HDMITX0_REF>,
4994 <&cru MCLK_I2S5_8CH_TX>,
4995 <&cru DCLK_VOP0>,
4996 <&cru DCLK_VOP1>,
4997 <&cru DCLK_VOP2>,
4998 <&cru DCLK_VOP3>,
5012 resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
5059 clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>,
5060 <&cru CLK_EDP0_200M>, <&hclk_vo1>;
5062 resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>;
5358 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
5359 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
5360 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
5393 resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
5412 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
5413 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
5414 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
5447 resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
5476 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
5477 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
5478 <&cru CLK_GMAC1_PTP_REF>;
5482 resets = <&cru SRST_A_GMAC1>;
5520 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
5521 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
5522 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
5535 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
5536 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
5537 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
5551 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
5553 assigned-clocks = <&cru SCLK_SFC>;
5565 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
5579 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
5580 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
5594 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
5596 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
5597 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
5598 <&cru TMCLK_EMMC>;
5600 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
5601 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
5602 <&cru SRST_T_EMMC>;
5635 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
5637 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
5638 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
5642 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
5663 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
5667 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
5689 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
5691 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
5692 assigned-clock-parents = <&cru PLL_AUPLL>;
5711 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
5713 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
5714 assigned-clock-parents = <&cru PLL_AUPLL>;
5732 clocks = <&cru MCLK_PDM0>, <&cru HCLK_PDM0>;
5751 clocks = <&cru MCLK_PDM1>, <&cru HCLK_PDM1>;
5753 assigned-clocks = <&cru MCLK_PDM1>;
5754 assigned-clock-parents = <&cru PLL_AUPLL>;
5774 clocks = <&cru HCLK_VAD>;
5791 clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>;
5792 assigned-clocks = <&cru CLK_SPDIF0_SRC>;
5793 assigned-clock-parents = <&cru PLL_AUPLL>;
5808 clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>;
5809 assigned-clocks = <&cru CLK_SPDIF1_SRC>;
5810 assigned-clock-parents = <&cru PLL_AUPLL>;
5821 clocks = <&cru CLK_DAC_ACDCDIG>, <&cru PCLK_ACDCDIG>;
5824 resets = <&cru SRST_DAC_ACDCDIG>;
5870 clocks = <&cru ACLK_DMAC0>;
5881 clocks = <&cru ACLK_DMAC1>;
5891 clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>;
5893 resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>;
5906 clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>;
5908 resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>;
5921 clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>;
5923 resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>;
5936 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>;
5938 resets = <&cru SRST_D_DECOM>;
5946 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
5959 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
5972 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
5985 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
5998 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
6012 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
6019 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
6031 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
6047 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
6063 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
6079 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
6093 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
6107 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
6121 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
6135 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
6149 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
6163 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
6177 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
6191 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
6205 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
6222 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
6234 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
6246 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
6259 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
6271 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
6283 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
6295 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
6308 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
6320 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
6332 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
6344 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
6357 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
6366 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
6368 assigned-clocks = <&cru CLK_TSADC>;
6370 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>;
6374 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
6387 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
6389 resets = <&cru SRST_P_SARADC>;
6402 clocks = <&cru PCLK_MAILBOX0>;
6416 clocks = <&cru PCLK_MAILBOX1>;
6425 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
6438 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
6451 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
6467 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
6482 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
6483 <&cru CLK_OTPC_ARB>, <&cru CLK_OTP_PHY_G>;
6485 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
6486 <&cru SRST_OTPC_ARB>;
6567 clocks = <&cru PCLK_MAILBOX2>;
6578 clocks = <&cru ACLK_DMAC2>;
6587 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
6589 resets = <&cru SRST_P_HDPTX0>, <&cru SRST_HDPTX0_INIT>,
6590 <&cru SRST_HDPTX0_CMN>, <&cru SRST_HDPTX0_LANE>;
6600 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
6602 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
6603 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
6604 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
6605 <&cru SRST_HDPTX0_LCPLL>;
6625 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
6626 <&cru CLK_USBDP_PHY0_IMMORTAL>,
6627 <&cru PCLK_USBDPPHY0>,
6630 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
6631 <&cru SRST_USBDP_COMBO_PHY0_CMN>,
6632 <&cru SRST_USBDP_COMBO_PHY0_LANE>,
6633 <&cru SRST_USBDP_COMBO_PHY0_PCS>,
6634 <&cru SRST_P_USBDPPHY0>;
6653 clocks = <&cru PCLK_MIPI_DCPHY0>,
6654 <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
6656 resets = <&cru SRST_M_MIPI_DCPHY0>,
6657 <&cru SRST_P_MIPI_DCPHY0>,
6658 <&cru SRST_P_MIPI_DCPHY0_GRF>,
6659 <&cru SRST_S_MIPI_DCPHY0>;
6669 clocks = <&cru PCLK_MIPI_DCPHY1>,
6670 <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
6672 resets = <&cru SRST_M_MIPI_DCPHY1>,
6673 <&cru SRST_P_MIPI_DCPHY1>,
6674 <&cru SRST_P_MIPI_DCPHY1_GRF>,
6675 <&cru SRST_S_MIPI_DCPHY1>;
6684 clocks = <&cru PCLK_CSIPHY0>;
6686 resets = <&cru SRST_CSIPHY0>, <&cru SRST_P_CSIPHY0>;
6696 clocks = <&cru PCLK_CSIPHY1>;
6698 resets = <&cru SRST_CSIPHY1>, <&cru SRST_P_CSIPHY1>;
6709 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
6710 <&cru PCLK_PHP_ROOT>;
6712 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
6714 resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>;
6725 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
6726 <&cru PCLK_PHP_ROOT>;
6728 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
6730 resets = <&cru SRST_P_PCIE2_PHY2>, <&cru SRST_REF_PIPE_PHY2>;
6765 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
6778 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
6791 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
6804 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
6817 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;