Lines Matching +full:0 +full:xfea80000
89 #clock-cells = <0>;
96 #clock-cells = <0>;
103 #clock-cells = <0>;
110 reg = <0 0xfd7c08ec 0 0x10>;
114 #clock-cells = <0>;
119 reg = <0 0xfd7c08b0 0 0x10>;
123 #clock-cells = <0>;
128 reg = <0 0xfd7c08dc 0 0x10>;
132 #clock-cells = <0>;
137 reg = <0 0xfd7c08a8 0 0x10>;
141 #clock-cells = <0>;
146 reg = <0 0xfd7c087c 0 0x10>;
150 #clock-cells = <0>;
155 reg = <0 0xfd7c08a8 0 0x10>;
159 #clock-cells = <0>;
164 reg = <0 0xfd7c0868 0 0x10>;
168 #clock-cells = <0>;
173 reg = <0 0xfd7c0868 0 0x10>;
177 #clock-cells = <0>;
182 reg = <0 0xfd7c08a0 0 0x10>;
186 #clock-cells = <0>;
191 reg = <0 0xfd7c08a0 0 0x10>;
195 #clock-cells = <0>;
200 reg = <0 0xfd7c08a4 0 0x10>;
204 #clock-cells = <0>;
209 reg = <0 0xfd7c08a4 0 0x10>;
213 #clock-cells = <0>;
218 reg = <0 0xfd7c08b0 0 0x10>;
222 #clock-cells = <0>;
227 reg = <0 0xfd7c08c0 0 0x10>;
231 #clock-cells = <0>;
236 reg = <0 0xfd7c08c0 0 0x10>;
240 #clock-cells = <0>;
245 reg = <0 0xfd7c08dc 0 0x10>;
249 #clock-cells = <0>;
254 reg = <0 0xfd7c08ec 0 0x10>;
258 #clock-cells = <0>;
263 reg = <0 0xfd7c0910 0 0x10>;
267 #clock-cells = <0>;
272 reg = <0 0xfd7c0910 0 0x10>;
276 #clock-cells = <0>;
281 reg = <0 0xfd7c092c 0 0x10>;
285 #clock-cells = <0>;
290 reg = <0x0 0xfd7c08dc 0x0 0x4>;
293 #clock-cells = <0>;
298 reg = <0x0 0xfd7c08ec 0x0 0x4>;
301 #clock-cells = <0>;
306 #clock-cells = <0>;
307 clock-frequency = <0>;
313 #clock-cells = <0>;
314 clock-frequency = <0>;
320 #clock-cells = <0>;
321 clock-frequency = <0>;
327 #clock-cells = <0>;
328 clock-frequency = <0>;
334 reg = <0 0xfd58c318 0 0x4>;
336 #clock-cells = <0>;
338 rockchip,bit-shift = <0>;
344 reg = <0 0xfd58c318 0 0x4>;
346 #clock-cells = <0>;
354 reg = <0 0xfd58a000 0 0x4>;
356 #clock-cells = <0>;
363 reg = <0 0xfd58c318 0 0x4>;
365 #clock-cells = <0>;
373 reg = <0 0xfd58c318 0 0x4>;
375 #clock-cells = <0>;
384 #size-cells = <0>;
419 cpu_l0: cpu@0 {
422 reg = <0x0>;
442 reg = <0x100>;
460 reg = <0x200>;
478 reg = <0x300>;
496 reg = <0x400>;
516 reg = <0x500>;
534 reg = <0x600>;
554 reg = <0x700>;
574 arm,psci-suspend-param = <0x0010000>;
662 rockchip,pvtm-hw = <0x06>;
664 0 1365 0
673 0 1410 0
682 rockchip,pvtm-offset = <0x64>;
710 opp-supported-hw = <0xf9 0xffff>;
717 opp-supported-hw = <0xf9 0xffff>;
724 opp-supported-hw = <0xf9 0xffff>;
731 opp-supported-hw = <0xf9 0xffff>;
738 opp-supported-hw = <0xf9 0xffff>;
757 opp-supported-hw = <0xf9 0xffff>;
777 opp-supported-hw = <0xf9 0xffff>;
796 opp-supported-hw = <0xf9 0xffff>;
817 opp-supported-hw = <0x06 0xffff>;
824 opp-supported-hw = <0x06 0xffff>;
831 opp-supported-hw = <0x06 0xffff>;
838 opp-supported-hw = <0x06 0xffff>;
845 opp-supported-hw = <0x06 0xffff>;
852 opp-supported-hw = <0x04 0xffff>;
863 opp-supported-hw = <0x06 0xffff>;
877 opp-supported-hw = <0x06 0xffff>;
896 opp-supported-hw = <0x06 0xffff>;
924 rockchip,pvtm-hw = <0x06>;
926 0 1539 0
936 0 1595 0
946 rockchip,pvtm-offset = <0x18>;
975 opp-supported-hw = <0xf9 0xffff>;
983 opp-supported-hw = <0xf9 0xffff>;
990 opp-supported-hw = <0xf9 0xffff>;
997 opp-supported-hw = <0xf9 0xffff>;
1004 opp-supported-hw = <0xf9 0xffff>;
1011 opp-supported-hw = <0xf9 0xffff>;
1030 opp-supported-hw = <0xf9 0xffff>;
1049 opp-supported-hw = <0xf9 0xffff>;
1070 opp-supported-hw = <0xf9 0xffff>;
1091 opp-supported-hw = <0xf9 0xffff>;
1112 opp-supported-hw = <0xf9 0x13>;
1119 opp-supported-hw = <0xf9 0x24>;
1126 opp-supported-hw = <0xf9 0x48>;
1133 opp-supported-hw = <0xf9 0x80>;
1142 opp-supported-hw = <0x06 0xffff>;
1149 opp-supported-hw = <0x06 0xffff>;
1156 opp-supported-hw = <0x06 0xffff>;
1163 opp-supported-hw = <0x06 0xffff>;
1170 opp-supported-hw = <0x06 0xffff>;
1177 opp-supported-hw = <0x06 0xffff>;
1187 opp-supported-hw = <0x06 0xffff>;
1206 opp-supported-hw = <0x06 0xffff>;
1227 opp-supported-hw = <0x06 0xffff>;
1257 rockchip,pvtm-hw = <0x06>;
1259 0 1539 0
1269 0 1595 0
1279 rockchip,pvtm-offset = <0x18>;
1308 opp-supported-hw = <0xf9 0x0ffff>;
1316 opp-supported-hw = <0xf9 0xffff>;
1323 opp-supported-hw = <0xf9 0xffff>;
1330 opp-supported-hw = <0xf9 0xffff>;
1337 opp-supported-hw = <0xf9 0xffff>;
1344 opp-supported-hw = <0xf9 0xffff>;
1363 opp-supported-hw = <0xf9 0xffff>;
1382 opp-supported-hw = <0xf9 0xffff>;
1403 opp-supported-hw = <0xf9 0xffff>;
1424 opp-supported-hw = <0xf9 0xffff>;
1441 opp-supported-hw = <0xf9 0x13>;
1448 opp-supported-hw = <0xf9 0x24>;
1455 opp-supported-hw = <0xf9 0x48>;
1462 opp-supported-hw = <0xf9 0x80>;
1471 opp-supported-hw = <0x06 0xffff>;
1478 opp-supported-hw = <0x06 0xffff>;
1485 opp-supported-hw = <0x06 0xffff>;
1492 opp-supported-hw = <0x06 0xffff>;
1499 opp-supported-hw = <0x06 0xffff>;
1506 opp-supported-hw = <0x06 0xffff>;
1516 opp-supported-hw = <0x06 0xffff>;
1535 opp-supported-hw = <0x06 0xffff>;
1556 opp-supported-hw = <0x06 0xffff>;
1760 1 31 0
1771 opp-supported-hw = <0xf9 0xffff>;
1783 opp-supported-hw = <0xf9 0xffff>;
1795 opp-supported-hw = <0xf9 0xffff>;
1807 opp-supported-hw = <0xf9 0xffff>;
1821 opp-supported-hw = <0x06 0xffff>;
1827 opp-supported-hw = <0x06 0xffff>;
1833 opp-supported-hw = <0x06 0xffff>;
1845 opp-supported-hw = <0x06 0xffff>;
1862 arm,smc-id = <0x82000010>;
1864 #size-cells = <0>;
1867 reg = <0x14>;
1879 reg = <0x16>;
2169 rockchip,sleep-debug-en = <0>;
2171 (0
2179 (0
2197 thermal-sensors = <&tsadc 0>;
2199 threshold: trip-point-0 {
2288 reg = <0x0 0x0010f000 0x0 0x100>;
2291 ranges = <0 0x0 0x0010f000 0x100>;
2293 scmi_shmem: sram@0 {
2295 reg = <0x0 0x100>;
2301 reg = <0x0 0xfb000000 0x0 0x200000>;
2331 rockchip,pvtm-hw = <0x04>;
2333 0 799 0
2341 0 815 0
2349 rockchip,pvtm-offset = <0x1c>;
2377 opp-supported-hw = <0xf9 0xffff>;
2383 opp-supported-hw = <0xf9 0xffff>;
2389 opp-supported-hw = <0xf9 0xffff>;
2395 opp-supported-hw = <0xf9 0xffff>;
2401 opp-supported-hw = <0xf9 0xffff>;
2415 opp-supported-hw = <0xf9 0xffff>;
2431 opp-supported-hw = <0xf9 0xffff>;
2447 opp-supported-hw = <0xf9 0xffff>;
2465 opp-supported-hw = <0x06 0xffff>;
2471 opp-supported-hw = <0x06 0xffff>;
2477 opp-supported-hw = <0x06 0xffff>;
2483 opp-supported-hw = <0x06 0xffff>;
2489 opp-supported-hw = <0x06 0xffff>;
2496 opp-supported-hw = <0x04 0xffff>;
2513 opp-supported-hw = <0x02 0xffff>;
2519 opp-supported-hw = <0x02 0xffff>;
2535 opp-supported-hw = <0x02 0xffff>;
2564 reg = <0x0 0xfc000000 0x0 0x400000>;
2587 reg = <0x0 0xfc800000 0x0 0x40000>;
2600 reg = <0x0 0xfc840000 0x0 0x40000>;
2612 reg = <0x0 0xfc880000 0x0 0x40000>;
2625 reg = <0x0 0xfc8c0000 0x0 0x40000>;
2637 reg = <0x0 0xfc900000 0x0 0x200000>;
2649 reg = <0x0 0xfcb00000 0x0 0x200000>;
2672 reg = <0x0 0xfcd00000 0x0 0x400000>;
2692 reg = <0x0 0xfd588000 0x0 0x2000>;
2696 offset = <0x80>;
2712 reg = <0x0 0xfd58a000 0x0 0x2000>;
2717 reg = <0x0 0xfd58c000 0x0 0x1000>;
2722 pinctrl-0 = <&bt1120_pins>;
2727 #size-cells = <0>;
2729 port@0 {
2730 reg = <0>;
2732 #size-cells = <0>;
2746 reg = <0x0 0xfd590000 0x0 0x100>;
2751 reg = <0x0 0xfd592000 0x0 0x100>;
2756 reg = <0x0 0xfd594000 0x0 0x100>;
2761 reg = <0x0 0xfd598000 0x0 0x100>;
2766 reg = <0x0 0xfd5a0000 0x0 0x100>;
2771 reg = <0x0 0xfd5a2000 0x0 0x100>;
2776 reg = <0x0 0xfd5a4000 0x0 0x2000>;
2781 reg = <0x0 0xfd5a6000 0x0 0x2000>;
2787 reg = <0x0 0xfd5a8000 0x0 0x100>;
2793 reg = <0x0 0xfd5ac000 0x0 0x4000>;
2798 reg = <0x0 0xfd5b0000 0x0 0x1000>;
2803 reg = <0x0 0xfd5b4000 0x0 0x1000>;
2808 reg = <0x0 0xfd5b5000 0x0 0x1000>;
2813 reg = <0x0 0xfd5bc000 0x0 0x100>;
2818 reg = <0x0 0xfd5c4000 0x0 0x100>;
2823 reg = <0x0 0xfd5c8000 0x0 0x4000>;
2829 reg = <0x0 0xfd5d0000 0x0 0x4000>;
2833 u2phy0: usb2-phy@0 {
2835 reg = <0x0 0x10>;
2842 #clock-cells = <0>;
2847 #phy-cells = <0>;
2856 reg = <0x0 0xfd5d8000 0x0 0x4000>;
2862 reg = <0x8000 0x10>;
2869 #clock-cells = <0>;
2873 #phy-cells = <0>;
2882 reg = <0x0 0xfd5dc000 0x0 0x4000>;
2888 reg = <0xc000 0x10>;
2895 #clock-cells = <0>;
2899 #phy-cells = <0>;
2907 reg = <0x0 0xfd5e0000 0x0 0x100>;
2912 reg = <0x0 0xfd5e8000 0x0 0x4000>;
2917 reg = <0x0 0xfd5ec000 0x0 0x4000>;
2922 reg = <0x0 0xfd5f0000 0x0 0x10000>;
2928 reg = <0x0 0xfd7c0000 0x0 0x5c000>;
2960 reg = <0x0 0xfd880000 0x0 0x1000>;
2965 pinctrl-0 = <&i2c0m0_xfer>;
2967 #size-cells = <0>;
2973 reg = <0x0 0xfd890000 0x0 0x100>;
2981 pinctrl-0 = <&uart0m1_xfer>;
2987 reg = <0x0 0xfd8b0000 0x0 0x10>;
2991 pinctrl-0 = <&pwm0m0_pins>;
2999 reg = <0x0 0xfd8b0010 0x0 0x10>;
3003 pinctrl-0 = <&pwm1m0_pins>;
3011 reg = <0x0 0xfd8b0020 0x0 0x10>;
3015 pinctrl-0 = <&pwm2m0_pins>;
3023 reg = <0x0 0xfd8b0030 0x0 0x10>;
3028 pinctrl-0 = <&pwm3m0_pins>;
3036 reg = <0x0 0xfd8d8000 0x0 0x400>;
3042 #size-cells = <0>;
3049 #size-cells = <0>;
3054 #size-cells = <0>;
3094 #size-cells = <0>;
3116 #size-cells = <0>;
3139 #size-cells = <0>;
3199 #size-cells = <0>;
3233 #size-cells = <0>;
3317 reg = <0x0 0xfda40000 0x0 0x100>;
3319 #size-cells = <0>;
3320 pvtm@0 {
3321 reg = <0>;
3329 reg = <0x0 0xfda50000 0x0 0x100>;
3331 #size-cells = <0>;
3341 reg = <0x0 0xfda60000 0x0 0x100>;
3343 #size-cells = <0>;
3353 reg = <0x0 0xfdaf0000 0x0 0x100>;
3355 #size-cells = <0>;
3367 reg = <0x0 0xfdb30000 0x0 0x100>;
3369 #size-cells = <0>;
3381 reg = <0x0 0xfdab0000 0x0 0x10000>,
3382 <0x0 0xfdac0000 0x0 0x10000>,
3383 <0x0 0xfdad0000 0x0 0x10000>;
3418 rockchip,pvtm-hw = <0x06>;
3420 0 799 0
3428 0 815 0
3436 rockchip,pvtm-offset = <0x50>;
3465 opp-supported-hw = <0xf9 0xffff>;
3481 opp-supported-hw = <0xf9 0xffff>;
3497 opp-supported-hw = <0xf9 0xffff>;
3513 opp-supported-hw = <0xf9 0xffff>;
3529 opp-supported-hw = <0xf9 0xffff>;
3541 opp-supported-hw = <0xf9 0xffff>;
3555 opp-supported-hw = <0xf9 0xffff>;
3571 opp-supported-hw = <0xf9 0xffff>;
3589 opp-supported-hw = <0x06 0xffff>;
3595 opp-supported-hw = <0x06 0xffff>;
3601 opp-supported-hw = <0x06 0xffff>;
3607 opp-supported-hw = <0x06 0xffff>;
3613 opp-supported-hw = <0x06 0xffff>;
3619 opp-supported-hw = <0x06 0xffff>;
3625 opp-supported-hw = <0x06 0xffff>;
3644 reg = <0x0 0xfdab9000 0x0 0x100>,
3645 <0x0 0xfdaba000 0x0 0x100>,
3646 <0x0 0xfdaca000 0x0 0x100>,
3647 <0x0 0xfdada000 0x0 0x100>;
3656 #iommu-cells = <0>;
3662 reg = <0x0 0xfdb50000 0x0 0x400>;
3667 rockchip,normal-rates = <594000000>, <0>;
3676 rockchip,taskqueue-node = <0>;
3677 rockchip,resetgroup-node = <0>;
3684 reg = <0x0 0xfdb50400 0x0 0x400>;
3689 rockchip,normal-rates = <594000000>, <0>;
3698 rockchip,taskqueue-node = <0>;
3699 rockchip,resetgroup-node = <0>;
3706 reg = <0x0 0xfdb50800 0x0 0x40>;
3712 #iommu-cells = <0>;
3718 reg = <0x0 0xfdb51000 0x0 0x200>;
3723 rockchip,normal-rates = <594000000>, <0>;
3733 rockchip,taskqueue-node = <0>;
3734 rockchip,resetgroup-node = <0>;
3740 reg = <0x0 0xfdb60000 0x0 0x1000>;
3752 reg = <0x0 0xfdb60f00 0x0 0x100>;
3758 #iommu-cells = <0>;
3764 reg = <0x0 0xfdb70000 0x0 0x1000>;
3776 reg = <0x0 0xfdb70f00 0x0 0x100>;
3782 #iommu-cells = <0>;
3788 reg = <0x0 0xfdb80000 0x0 0x1000>;
3799 reg = <0x0 0xfdb90000 0x0 0x400>;
3804 rockchip,normal-rates = <600000000>, <0>;
3819 reg = <0x0 0xfdb90480 0x0 0x40>;
3825 #iommu-cells = <0>;
3831 reg = <0x0 0xfdba0000 0x0 0x400>;
3836 rockchip,normal-rates = <594000000>, <0>;
3853 reg = <0x0 0xfdba0800 0x0 0x40>;
3859 #iommu-cells = <0>;
3865 reg = <0x0 0xfdba4000 0x0 0x400>;
3870 rockchip,normal-rates = <594000000>, <0>;
3887 reg = <0x0 0xfdba4800 0x0 0x40>;
3893 #iommu-cells = <0>;
3899 reg = <0x0 0xfdba8000 0x0 0x400>;
3904 rockchip,normal-rates = <594000000>, <0>;
3921 reg = <0x0 0xfdba8800 0x0 0x40>;
3927 #iommu-cells = <0>;
3933 reg = <0x0 0xfdbac000 0x0 0x400>;
3938 rockchip,normal-rates = <594000000>, <0>;
3955 reg = <0x0 0xfdbac800 0x0 0x40>;
3961 #iommu-cells = <0>;
3967 reg = <0x0 0xfdbb0000 0x0 0x500>;
3972 rockchip,normal-rates = <594000000>, <0>;
3988 reg = <0x0 0xfdbb0800 0x0 0x100>;
3993 #iommu-cells = <0>;
4000 reg = <0x0 0xfdbd0000 0x0 0x6000>;
4005 rockchip,normal-rates = <500000000>, <0>, <800000000>;
4023 reg = <0x0 0xfdbdf000 0x0 0x40>, <0x0 0xfdbdf040 0x0 0x40>;
4032 #iommu-cells = <0>;
4039 reg = <0x0 0xfdbe0000 0x0 0x6000>;
4044 rockchip,normal-rates = <500000000>, <0>, <800000000>;
4062 reg = <0x0 0xfdbef000 0x0 0x40>, <0x0 0xfdbef040 0x0 0x40>;
4071 #iommu-cells = <0>;
4082 1 8 0
4110 reg = <0x0 0xfdc30000 0x0 0x100>;
4127 reg = <0x0 0xfdc38100 0x0 0x400>, <0x0 0xfdc38000 0x0 0x100>;
4135 rockchip,normal-rates = <800000000>, <0>, <600000000>,
4149 rockchip,core-mask = <0x00010001>;
4154 rockchip,rcb-iova = <0xFFF00000 0x100000>;
4165 reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>;
4174 #iommu-cells = <0>;
4181 reg = <0x0 0xfdc48100 0x0 0x400>, <0x0 0xfdc48000 0x0 0x100>;
4189 rockchip,normal-rates = <800000000>, <0>, <600000000>,
4203 rockchip,core-mask = <0x00020002>;
4208 rockchip,rcb-iova = <0xFFE00000 0x100000>;
4219 reg = <0x0 0xfdc48700 0x0 0x40>, <0x0 0xfdc48740 0x0 0x40>;
4228 #iommu-cells = <0>;
4235 reg = <0x0 0xfdc70000 0x0 0x800>, <0x0 0xfdc80000 0x0 0x400>,
4236 <0x0 0xfdc90000 0x0 0x400>;
4257 reg = <0x0 0xfdca0000 0x0 0x600>;
4262 #iommu-cells = <0>;
4269 reg = <0x0 0xfdcb0000 0x0 0x10000>,
4270 <0x0 0xfdcc0000 0x0 0x10000>;
4291 reg = <0x0 0xfdcb0000 0x0 0x7f00>;
4308 reg = <0x0 0xfdcb7f00 0x0 0x100>, <0x0 0xfdcc7f00 0x0 0x100>;
4316 #iommu-cells = <0>;
4323 reg = <0x0 0xfdcb7f00 0x0 0x100>;
4329 #iommu-cells = <0>;
4336 reg = <0x0 0xfdcc0000 0x0 0x7f00>;
4353 reg = <0x0 0xfdcc7f00 0x0 0x100>;
4359 #iommu-cells = <0>;
4366 reg = <0x0 0xfdcd0000 0x0 0x0f00>;
4381 reg = <0x0 0xfdcd0f00 0x0 0x100>;
4387 #iommu-cells = <0>;
4394 reg = <0x0 0xfdcd8000 0x0 0x0f00>;
4409 reg = <0x0 0xfdcd8f00 0x0 0x100>;
4415 #iommu-cells = <0>;
4422 reg = <0x0 0xfdce0000 0x0 0x800>;
4453 reg = <0x0 0xfdce0800 0x0 0x100>,
4454 <0x0 0xfdce0900 0x0 0x100>;
4461 #iommu-cells = <0>;
4467 reg = <0x0 0xfdd10000 0x0 0x10000>;
4481 reg = <0x0 0xfdd20000 0x0 0x10000>;
4495 reg = <0x0 0xfdd30000 0x0 0x10000>;
4509 reg = <0x0 0xfdd40000 0x0 0x10000>;
4523 reg = <0x0 0xfdd50000 0x0 0x10000>;
4537 reg = <0x0 0xfdd60000 0x0 0x10000>;
4551 reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
4599 #size-cells = <0>;
4601 vp0: port@0 {
4603 #size-cells = <0>;
4604 reg = <0>;
4606 vp0_out_dp0: endpoint@0 {
4607 reg = <0>;
4624 #size-cells = <0>;
4627 vp1_out_dp0: endpoint@0 {
4628 reg = <0>;
4645 #size-cells = <0>;
4651 vp2_out_dp0: endpoint@0 {
4652 reg = <0>;
4679 #size-cells = <0>;
4682 vp3_out_dsi0: endpoint@0 {
4683 reg = <0>;
4702 reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
4707 #iommu-cells = <0>;
4715 reg = <0x0 0xfddb0000 0x0 0x1000>;
4724 #sound-dai-cells = <0>;
4730 reg = <0x0 0xfddc0000 0x0 0x1000>;
4736 dmas = <&dmac2 0>;
4742 #sound-dai-cells = <0>;
4748 reg = <0x0 0xfdde0000 0x0 0x1000>;
4757 #sound-dai-cells = <0>;
4763 reg = <0x0 0xfddf0000 0x0 0x1000>;
4777 #sound-dai-cells = <0>;
4783 reg = <0x0 0xfddfc000 0x0 0x1000>;
4795 #sound-dai-cells = <0>;
4801 reg = <0x0 0xfde08000 0x0 0x1000>;
4812 #sound-dai-cells = <0>;
4818 reg = <0x0 0xfde20000 0x0 0x10000>;
4829 #size-cells = <0>;
4834 #size-cells = <0>;
4836 dsi0_in: port@0 {
4837 reg = <0>;
4839 #size-cells = <0>;
4841 dsi0_in_vp2: endpoint@0 {
4842 reg = <0>;
4858 reg = <0x0 0xfde30000 0x0 0x10000>;
4869 #size-cells = <0>;
4874 #size-cells = <0>;
4876 dsi1_in: port@0 {
4877 reg = <0>;
4879 #size-cells = <0>;
4881 dsi1_in_vp2: endpoint@0 {
4882 reg = <0>;
4898 reg = <0x0 0xfde40000 0x0 0x80>;
4915 reg = <0x0 0xfde50000 0x0 0x4000>;
4931 #size-cells = <0>;
4933 port@0 {
4934 reg = <0>;
4936 #size-cells = <0>;
4938 dp0_in_vp0: endpoint@0 {
4939 reg = <0>;
4967 reg = <0x0 0xfde70000 0x0 0x80>;
4984 reg = <0x0 0xfde80000 0x0 0x20000>;
5016 pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>;
5022 #sound-dai-cells = <0>;
5027 #size-cells = <0>;
5029 hdmi0_in: port@0 {
5030 reg = <0>;
5032 #size-cells = <0>;
5034 hdmi0_in_vp0: endpoint@0 {
5035 reg = <0>;
5057 reg = <0x0 0xfdec0000 0x0 0x1000>;
5072 #size-cells = <0>;
5074 port@0 {
5075 reg = <0>;
5077 #size-cells = <0>;
5079 edp0_in_vp0: endpoint@0 {
5080 reg = <0>;
5108 reg = <0x0 0xfdf35000 0x0 0x20>;
5113 reg = <0x0 0xfdf35200 0x0 0x20>;
5118 reg = <0x0 0xfdf35400 0x0 0x20>;
5123 reg = <0x0 0xfdf35600 0x0 0x20>;
5128 reg = <0x0 0xfdf36000 0x0 0x20>;
5133 reg = <0x0 0xfdf39000 0x0 0x20>;
5138 reg = <0x0 0xfdf3d800 0x0 0x20>;
5143 reg = <0x0 0xfdf3e000 0x0 0x20>;
5148 reg = <0x0 0xfdf3e200 0x0 0x20>;
5153 reg = <0x0 0xfdf3e400 0x0 0x20>;
5158 reg = <0x0 0xfdf3e600 0x0 0x20>;
5163 reg = <0x0 0xfdf40000 0x0 0x20>;
5168 reg = <0x0 0xfdf40200 0x0 0x20>;
5173 reg = <0x0 0xfdf40400 0x0 0x20>;
5178 reg = <0x0 0xfdf40500 0x0 0x20>;
5183 reg = <0x0 0xfdf40600 0x0 0x20>;
5188 reg = <0x0 0xfdf40800 0x0 0x20>;
5193 reg = <0x0 0xfdf41000 0x0 0x20>;
5198 reg = <0x0 0xfdf41100 0x0 0x20>;
5203 reg = <0x0 0xfdf60000 0x0 0x20>;
5208 reg = <0x0 0xfdf60200 0x0 0x20>;
5213 reg = <0x0 0xfdf60400 0x0 0x20>;
5218 reg = <0x0 0xfdf61000 0x0 0x20>;
5223 reg = <0x0 0xfdf61200 0x0 0x20>;
5228 reg = <0x0 0xfdf61400 0x0 0x20>;
5233 reg = <0x0 0xfdf62000 0x0 0x20>;
5238 reg = <0x0 0xfdf63000 0x0 0x20>;
5243 reg = <0x0 0xfdf64000 0x0 0x20>;
5248 reg = <0x0 0xfdf66000 0x0 0x20>;
5253 reg = <0x0 0xfdf66200 0x0 0x20>;
5258 reg = <0x0 0xfdf66400 0x0 0x20>;
5263 reg = <0x0 0xfdf66600 0x0 0x20>;
5268 reg = <0x0 0xfdf66800 0x0 0x20>;
5273 reg = <0x0 0xfdf66a00 0x0 0x20>;
5278 reg = <0x0 0xfdf66c00 0x0 0x20>;
5283 reg = <0x0 0xfdf66e00 0x0 0x20>;
5288 reg = <0x0 0xfdf67000 0x0 0x20>;
5293 reg = <0x0 0xfdf67200 0x0 0x20>;
5298 reg = <0x0 0xfdf70000 0x0 0x20>;
5303 reg = <0x0 0xfdf71000 0x0 0x20>;
5308 reg = <0x0 0xfdf72000 0x0 0x20>;
5313 reg = <0x0 0xfdf72200 0x0 0x20>;
5318 reg = <0x0 0xfdf72400 0x0 0x20>;
5323 reg = <0x0 0xfdf80000 0x0 0x20>;
5328 reg = <0x0 0xfdf81000 0x0 0x20>;
5333 reg = <0x0 0xfdf81200 0x0 0x20>;
5338 reg = <0x0 0xfdf82000 0x0 0x20>;
5343 reg = <0x0 0xfdf82200 0x0 0x20>;
5348 reg = <0x00 0xfe060000 0x00 0x10000>;
5357 bus-range = <0x30 0x3f>;
5372 interrupt-map-mask = <0 0 0 7>;
5373 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
5374 <0 0 0 2 &pcie2x1l1_intc 1>,
5375 <0 0 0 3 &pcie2x1l1_intc 2>,
5376 <0 0 0 4 &pcie2x1l1_intc 3>;
5382 msi-map = <0x3000 &its0 0x3000 0x1000>;
5386 ranges = <0x00000800 0x0 0xf3000000 0x0 0xf3000000 0x0 0x100000
5387 0x81000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x100000
5388 0x82000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0xe00000
5389 0xc3000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>;
5390 reg = <0x0 0xfe180000 0x0 0x10000>,
5391 <0xa 0x40c00000 0x0 0x400000>;
5400 #address-cells = <0>;
5411 bus-range = <0x40 0x4f>;
5426 interrupt-map-mask = <0 0 0 7>;
5427 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
5428 <0 0 0 2 &pcie2x1l2_intc 1>,
5429 <0 0 0 3 &pcie2x1l2_intc 2>,
5430 <0 0 0 4 &pcie2x1l2_intc 3>;
5436 msi-map = <0x4000 &its0 0x4000 0x1000>;
5440 ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000
5441 0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000
5442 0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0xe00000
5443 0xc3000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>;
5444 reg = <0x0 0xfe190000 0x0 0x10000>,
5445 <0xa 0x41000000 0x0 0x400000>;
5454 #address-cells = <0>;
5463 reg = <0x0 0xfe1c0000 0x0 0x10000>;
5470 reg = <0x0 0xfe1c0000 0x0 0x10000>;
5496 #address-cells = <0x1>;
5497 #size-cells = <0x0>;
5503 snps,blen = <0 0 0 0 16 8 4>;
5519 reg = <0 0xfe210000 0 0x1000>;
5528 ports-implemented = <0x1>;
5534 reg = <0 0xfe230000 0 0x1000>;
5543 ports-implemented = <0x1>;
5549 reg = <0x0 0xfe2b0000 0x0 0x4000>;
5556 #size-cells = <0>;
5562 reg = <0x0 0xfe2c0000 0x0 0x4000>;
5567 fifo-depth = <0x100>;
5570 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
5577 reg = <0x0 0xfe2d0000 0x0 0x4000>;
5582 fifo-depth = <0x100>;
5585 pinctrl-0 = <&sdiom1_pins>;
5592 reg = <0x0 0xfe2e0000 0x0 0x10000>;
5610 reg = <0x0 0xfe370000 0x0 0x2000>;
5622 reg = <0x0 0xfe378000 0x0 0x200>;
5633 reg = <0x0 0xfe470000 0x0 0x1000>;
5639 dmas = <&dmac0 0>, <&dmac0 1>;
5646 pinctrl-0 = <&i2s0_sdi0
5655 #sound-dai-cells = <0>;
5661 reg = <0x0 0xfe480000 0x0 0x1000>;
5671 pinctrl-0 = <&i2s1m0_lrck
5681 #sound-dai-cells = <0>;
5687 reg = <0x0 0xfe490000 0x0 0x1000>;
5693 dmas = <&dmac1 0>, <&dmac1 1>;
5698 pinctrl-0 = <&i2s2m1_sdi
5703 #sound-dai-cells = <0>;
5709 reg = <0x0 0xfe4a0000 0x0 0x1000>;
5720 pinctrl-0 = <&i2s3_sdi
5725 #sound-dai-cells = <0>;
5731 reg = <0x0 0xfe4b0000 0x0 0x1000>;
5737 pinctrl-0 = <&pdm0m0_sdi0
5744 #sound-dai-cells = <0>;
5750 reg = <0x0 0xfe4c0000 0x0 0x1000>;
5759 pinctrl-0 = <&pdm1m0_sdi0
5766 #sound-dai-cells = <0>;
5772 reg = <0x0 0xfe4d0000 0x0 0x1000>;
5777 rockchip,audio-src = <0>;
5778 rockchip,det-channel = <0>;
5779 rockchip,mode = <0>;
5780 #sound-dai-cells = <0>;
5786 reg = <0x0 0xfe4e0000 0x0 0x1000>;
5796 pinctrl-0 = <&spdif0m0_tx>;
5797 #sound-dai-cells = <0>;
5803 reg = <0x0 0xfe4f0000 0x0 0x1000>;
5813 pinctrl-0 = <&spdif1m0_tx>;
5814 #sound-dai-cells = <0>;
5820 reg = <0x0 0xfe500000 0x0 0x1000>;
5829 pinctrl-0 = <&auddsm_pins>;
5830 #sound-dai-cells = <0>;
5836 reg = <0 0xfe5a0000 0 0x100>;
5848 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
5849 <0x0 0xfe680000 0 0x100000>; /* GICR */
5855 reg = <0x0 0xfe640000 0x0 0x20000>;
5861 reg = <0x0 0xfe660000 0x0 0x20000>;
5867 reg = <0x0 0xfea10000 0x0 0x4000>;
5878 reg = <0x0 0xfea30000 0x0 0x4000>;
5889 reg = <0x0 0xfea50000 0x0 0x1000>;
5896 pinctrl-0 = <&can0m0_pins>;
5904 reg = <0x0 0xfea60000 0x0 0x1000>;
5911 pinctrl-0 = <&can1m0_pins>;
5919 reg = <0x0 0xfea70000 0x0 0x1000>;
5926 pinctrl-0 = <&can2m0_pins>;
5934 reg = <0x0 0xfea80000 0x0 0x1000>;
5945 reg = <0x0 0xfea90000 0x0 0x1000>;
5950 pinctrl-0 = <&i2c1m0_xfer>;
5952 #size-cells = <0>;
5958 reg = <0x0 0xfeaa0000 0x0 0x1000>;
5963 pinctrl-0 = <&i2c2m0_xfer>;
5965 #size-cells = <0>;
5971 reg = <0x0 0xfeab0000 0x0 0x1000>;
5976 pinctrl-0 = <&i2c3m0_xfer>;
5978 #size-cells = <0>;
5984 reg = <0x0 0xfeac0000 0x0 0x1000>;
5989 pinctrl-0 = <&i2c4m0_xfer>;
5991 #size-cells = <0>;
5997 reg = <0x0 0xfead0000 0x0 0x1000>;
6002 pinctrl-0 = <&i2c5m0_xfer>;
6004 #size-cells = <0>;
6010 reg = <0x0 0xfeae0000 0x0 0x20>;
6018 reg = <0x0 0xfeaf0000 0x0 0x100>;
6027 reg = <0x0 0xfeb00000 0x0 0x1000>;
6030 #size-cells = <0>;
6036 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
6043 reg = <0x0 0xfeb10000 0x0 0x1000>;
6046 #size-cells = <0>;
6052 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
6059 reg = <0x0 0xfeb20000 0x0 0x1000>;
6062 #size-cells = <0>;
6068 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
6075 reg = <0x0 0xfeb30000 0x0 0x1000>;
6078 #size-cells = <0>;
6084 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
6091 reg = <0x0 0xfeb40000 0x0 0x100>;
6099 pinctrl-0 = <&uart1m1_xfer>;
6105 reg = <0x0 0xfeb50000 0x0 0x100>;
6113 pinctrl-0 = <&uart2m1_xfer>;
6119 reg = <0x0 0xfeb60000 0x0 0x100>;
6127 pinctrl-0 = <&uart3m1_xfer>;
6133 reg = <0x0 0xfeb70000 0x0 0x100>;
6141 pinctrl-0 = <&uart4m1_xfer>;
6147 reg = <0x0 0xfeb80000 0x0 0x100>;
6155 pinctrl-0 = <&uart5m1_xfer>;
6161 reg = <0x0 0xfeb90000 0x0 0x100>;
6169 pinctrl-0 = <&uart6m1_xfer>;
6175 reg = <0x0 0xfeba0000 0x0 0x100>;
6183 pinctrl-0 = <&uart7m1_xfer>;
6189 reg = <0x0 0xfebb0000 0x0 0x100>;
6197 pinctrl-0 = <&uart8m1_xfer>;
6203 reg = <0x0 0xfebc0000 0x0 0x100>;
6211 pinctrl-0 = <&uart9m1_xfer>;
6217 reg = <0x0 0xfebd0000 0x0 0x10>;
6221 pinctrl-0 = <&pwm4m0_pins>;
6229 reg = <0x0 0xfebd0010 0x0 0x10>;
6233 pinctrl-0 = <&pwm5m0_pins>;
6241 reg = <0x0 0xfebd0020 0x0 0x10>;
6245 pinctrl-0 = <&pwm6m0_pins>;
6253 reg = <0x0 0xfebd0030 0x0 0x10>;
6258 pinctrl-0 = <&pwm7m0_pins>;
6266 reg = <0x0 0xfebe0000 0x0 0x10>;
6270 pinctrl-0 = <&pwm8m0_pins>;
6278 reg = <0x0 0xfebe0010 0x0 0x10>;
6282 pinctrl-0 = <&pwm9m0_pins>;
6290 reg = <0x0 0xfebe0020 0x0 0x10>;
6294 pinctrl-0 = <&pwm10m0_pins>;
6302 reg = <0x0 0xfebe0030 0x0 0x10>;
6307 pinctrl-0 = <&pwm11m0_pins>;
6315 reg = <0x0 0xfebf0000 0x0 0x10>;
6319 pinctrl-0 = <&pwm12m0_pins>;
6327 reg = <0x0 0xfebf0010 0x0 0x10>;
6331 pinctrl-0 = <&pwm13m0_pins>;
6339 reg = <0x0 0xfebf0020 0x0 0x10>;
6343 pinctrl-0 = <&pwm14m0_pins>;
6351 reg = <0x0 0xfebf0030 0x0 0x10>;
6356 pinctrl-0 = <&pwm15m0_pins>;
6364 reg = <0x0 0xfec00000 0x0 0x400>;
6374 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
6375 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
6377 pinctrl-0 = <&tsadc_gpio_func>;
6384 reg = <0x0 0xfec10000 0x0 0x10000>;
6397 reg = <0x0 0xfec60000 0x0 0x200>;
6411 reg = <0x0 0xfec70000 0x0 0x200>;
6424 reg = <0x0 0xfec80000 0x0 0x1000>;
6429 pinctrl-0 = <&i2c6m0_xfer>;
6431 #size-cells = <0>;
6437 reg = <0x0 0xfec90000 0x0 0x1000>;
6442 pinctrl-0 = <&i2c7m0_xfer>;
6444 #size-cells = <0>;
6450 reg = <0x0 0xfeca0000 0x0 0x1000>;
6455 pinctrl-0 = <&i2c8m0_xfer>;
6457 #size-cells = <0>;
6463 reg = <0x0 0xfecb0000 0x0 0x1000>;
6466 #size-cells = <0>;
6472 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
6479 reg = <0x0 0xfecc0000 0x0 0x400>;
6491 reg = <0x02 0x2>;
6494 reg = <0x05 0x1>;
6495 bits = <0 1>;
6498 reg = <0x06 0x1>;
6502 reg = <0x06 0x1>;
6503 bits = <0 5>;
6506 reg = <0x07 0x10>;
6509 reg = <0x1c 0x1>;
6513 reg = <0x17 0x1>;
6516 reg = <0x18 0x1>;
6519 reg = <0x19 0x1>;
6522 reg = <0x1a 0x1>;
6525 reg = <0x1b 0x1>;
6528 reg = <0x28 0x1>;
6531 reg = <0x29 0x1>;
6534 reg = <0x3d 0x6>;
6537 reg = <0x43 0x6>;
6540 reg = <0x49 0x6>;
6543 reg = <0x4f 0x6>;
6546 reg = <0x55 0x6>;
6549 reg = <0x5b 0x6>;
6552 reg = <0x61 0x6>;
6555 reg = <0x67 0x6>;
6562 reg = <0x0 0xfece0000 0x0 0x200>;
6575 reg = <0x0 0xfed10000 0x0 0x4000>;
6586 reg = <0x0 0xfed60000 0x0 0x2000>;
6593 #phy-cells = <0>;
6599 reg = <0x0 0xfed60000 0x0 0x2000>;
6609 #phy-cells = <0>;
6613 #clock-cells = <0>;
6620 reg = <0x0 0xfed80000 0x0 0x10000>;
6639 #phy-cells = <0>;
6644 #phy-cells = <0>;
6651 reg = <0x0 0xfeda0000 0x0 0x10000>;
6661 #phy-cells = <0>;
6667 reg = <0x0 0xfedb0000 0x0 0x10000>;
6677 #phy-cells = <0>;
6683 reg = <0x0 0xfedc0000 0x0 0x8000>;
6695 reg = <0x0 0xfedc8000 0x0 0x8000>;
6707 reg = <0x0 0xfee00000 0x0 0x100>;
6723 reg = <0x0 0xfee20000 0x0 0x100>;
6734 rockchip,pcie1ln-sel-bits = <0x100 1 1 0>;
6740 reg = <0x0 0xff001000 0x0 0xef000>;
6744 ranges = <0x0 0x0 0xff001000 0xef000>;
6746 rkvdec0_sram: rkvdec-sram@0 {
6747 reg = <0x0 0x78000>;
6750 reg = <0x78000 0x77000>;
6763 reg = <0x0 0xfd8a0000 0x0 0x100>;
6769 gpio-ranges = <&pinctrl 0 0 32>;
6776 reg = <0x0 0xfec20000 0x0 0x100>;
6782 gpio-ranges = <&pinctrl 0 32 32>;
6789 reg = <0x0 0xfec30000 0x0 0x100>;
6795 gpio-ranges = <&pinctrl 0 64 32>;
6802 reg = <0x0 0xfec40000 0x0 0x100>;
6808 gpio-ranges = <&pinctrl 0 96 32>;
6815 reg = <0x0 0xfec50000 0x0 0x100>;
6821 gpio-ranges = <&pinctrl 0 128 32>;