Lines Matching full:cru
94 clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
95 <&cru ACLK_USB3OTG1>;
107 resets = <&cru SRST_A_USB3OTG1>;
150 resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
152 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
178 clocks = <&cru MCLK_SPDIF5>, <&cru HCLK_SPDIF5_DP1>;
179 assigned-clocks = <&cru CLK_SPDIF5_DP1_SRC>;
180 assigned-clock-parents = <&cru PLL_AUPLL>;
190 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
192 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
193 assigned-clock-parents = <&cru PLL_AUPLL>;
197 resets = <&cru SRST_M_I2S8_8CH_TX>;
211 clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>;
212 assigned-clocks = <&cru CLK_SPDIF4_SRC>;
213 assigned-clock-parents = <&cru PLL_AUPLL>;
223 clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
225 assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
226 assigned-clock-parents = <&cru PLL_GPLL>;
230 resets = <&cru SRST_M_I2S6_8CH_TX>;
243 clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
245 assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
246 assigned-clock-parents = <&cru PLL_AUPLL>;
250 resets = <&cru SRST_M_I2S7_8CH_RX>;
261 clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
263 assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
264 assigned-clock-parents = <&cru PLL_AUPLL>;
268 resets = <&cru SRST_M_I2S10_8CH_RX>;
279 clocks = <&cru MCLK_SPDIFRX1>, <&cru HCLK_SPDIFRX1>;
281 assigned-clocks = <&cru MCLK_SPDIFRX1>;
282 assigned-clock-parents = <&cru PLL_AUPLL>;
286 resets = <&cru SRST_M_SPDIFRX1>;
296 clocks = <&cru MCLK_SPDIFRX2>, <&cru HCLK_SPDIFRX2>;
298 assigned-clocks = <&cru MCLK_SPDIFRX2>;
299 assigned-clock-parents = <&cru PLL_AUPLL>;
303 resets = <&cru SRST_M_SPDIFRX2>;
313 clocks = <&cru PCLK_DP1>, <&cru CLK_AUX16M_1>,
314 <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_SPDIF5_DP1>,
315 <&hclk_vo0>, <&cru CLK_DP1>;
317 assigned-clocks = <&cru CLK_AUX16M_1>;
319 resets = <&cru SRST_DP1>;
369 clocks = <&cru PCLK_HDMITX1>,
370 <&cru CLK_HDMIHDP1>,
371 <&cru CLK_HDMITX1_EARC>,
372 <&cru CLK_HDMITX1_REF>,
373 <&cru MCLK_I2S6_8CH_TX>,
374 <&cru DCLK_VOP0>,
375 <&cru DCLK_VOP1>,
376 <&cru DCLK_VOP2>,
377 <&cru DCLK_VOP3>,
391 resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>;
438 clocks = <&cru CLK_EDP1_24M>, <&cru PCLK_EDP1>,
439 <&cru CLK_EDP1_200M>, <&hclk_vo1>;
441 resets = <&cru SRST_EDP1_24M>, <&cru SRST_P_EDP1>;
496 clocks = <&cru ACLK_HDMIRX>,
497 <&cru CLK_HDMIRX_AUD>,
498 <&cru CLK_CR_PARA>,
499 <&cru PCLK_HDMIRX>,
500 <&cru CLK_HDMIRX_REF>,
501 <&cru PCLK_S_HDMIRX>,
510 resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>,
511 <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>;
523 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
524 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
525 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
559 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
578 clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
579 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
580 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
614 resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
633 clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
634 <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
635 <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
668 resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
697 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
698 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
699 <&cru CLK_GMAC0_PTP_REF>;
703 resets = <&cru SRST_A_GMAC0>;
741 clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
742 <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
743 <&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
756 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
758 resets = <&cru SRST_P_HDPTX1>, <&cru SRST_HDPTX1_INIT>,
759 <&cru SRST_HDPTX1_CMN>, <&cru SRST_HDPTX1_LANE>;
769 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
771 resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>,
772 <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,
773 <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>,
774 <&cru SRST_HDPTX1_LCPLL>;
795 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
796 <&cru CLK_USBDP_PHY1_IMMORTAL>,
797 <&cru PCLK_USBDPPHY1>,
800 resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
801 <&cru SRST_USBDP_COMBO_PHY1_CMN>,
802 <&cru SRST_USBDP_COMBO_PHY1_LANE>,
803 <&cru SRST_USBDP_COMBO_PHY1_PCS>,
804 <&cru SRST_P_USBDPPHY1>;
823 clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
824 <&cru PCLK_PHP_ROOT>;
826 assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
828 resets = <&cru SRST_P_PCIE2_PHY1>, <&cru SRST_REF_PIPE_PHY1>;
840 clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
842 resets = <&cru SRST_PCIE30_PHY>;