Lines Matching +full:0 +full:x40800000
104 reg = <0x0 0xfc400000 0x0 0x400000>;
126 reg = <0x0 0xfd5b8000 0x0 0x10000>;
131 reg = <0x0 0xfd5c0000 0x0 0x100>;
136 reg = <0x0 0xfd5cc000 0x0 0x4000>;
142 reg = <0x0 0xfd5d4000 0x0 0x4000>;
148 reg = <0x4000 0x10>;
155 #clock-cells = <0>;
160 #phy-cells = <0>;
168 reg = <0x0 0xfd5e4000 0x0 0x100>;
173 reg = <0x0 0xfddb8000 0x0 0x1000>;
182 #sound-dai-cells = <0>;
188 reg = <0x0 0xfddc8000 0x0 0x1000>;
200 #sound-dai-cells = <0>;
206 reg = <0x0 0xfdde8000 0x0 0x1000>;
215 #sound-dai-cells = <0>;
221 reg = <0x0 0xfddf4000 0x0 0x1000>;
235 #sound-dai-cells = <0>;
241 reg = <0x0 0xfddf8000 0x0 0x1000>;
253 #sound-dai-cells = <0>;
259 reg = <0x0 0xfde00000 0x0 0x1000>;
271 #sound-dai-cells = <0>;
277 reg = <0x0 0xfde10000 0x0 0x1000>;
288 #sound-dai-cells = <0>;
294 reg = <0x0 0xfde18000 0x0 0x1000>;
305 #sound-dai-cells = <0>;
311 reg = <0x0 0xfde60000 0x0 0x4000>;
327 #size-cells = <0>;
329 port@0 {
330 reg = <0>;
332 #size-cells = <0>;
334 dp1_in_vp0: endpoint@0 {
335 reg = <0>;
363 reg = <0x0 0xfdea0000 0x0 0x20000>;
395 pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda>;
401 #sound-dai-cells = <0>;
406 #size-cells = <0>;
408 hdmi1_in: port@0 {
409 reg = <0>;
411 #size-cells = <0>;
413 hdmi1_in_vp0: endpoint@0 {
414 reg = <0>;
436 reg = <0x0 0xfded0000 0x0 0x1000>;
451 #size-cells = <0>;
453 port@0 {
454 reg = <0>;
456 #size-cells = <0>;
458 edp1_in_vp0: endpoint@0 {
459 reg = <0>;
487 reg = <0x0 0xfdee0000 0x0 0x6000>;
513 pinctrl-0 = <&hdmim1_rx>;
522 bus-range = <0x00 0x0f>;
537 interrupt-map-mask = <0 0 0 7>;
538 interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
539 <0 0 0 2 &pcie3x4_intc 1>,
540 <0 0 0 3 &pcie3x4_intc 2>,
541 <0 0 0 4 &pcie3x4_intc 3>;
542 linux,pci-domain = <0>;
547 msi-map = <0x0000 &its1 0x0000 0x1000>;
552 ranges = <0x00000800 0x0 0xf0000000 0x0 0xf0000000 0x0 0x100000
553 0x81000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x100000
554 0x82000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0xe00000
555 0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
556 reg = <0x0 0xfe150000 0x0 0x10000>,
557 <0xa 0x40000000 0x0 0x400000>;
566 #address-cells = <0>;
577 bus-range = <0x10 0x1f>;
592 interrupt-map-mask = <0 0 0 7>;
593 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
594 <0 0 0 2 &pcie3x2_intc 1>,
595 <0 0 0 3 &pcie3x2_intc 2>,
596 <0 0 0 4 &pcie3x2_intc 3>;
602 msi-map = <0x1000 &its1 0x1000 0x1000>;
607 ranges = <0x00000800 0x0 0xf1000000 0x0 0xf1000000 0x0 0x100000
608 0x81000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x100000
609 0x82000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0xe00000
610 0xc3000000 0x9 0x40000000 0x9 0x40000000 0x0 0x40000000>;
611 reg = <0x0 0xfe160000 0x0 0x10000>,
612 <0xa 0x40400000 0x0 0x400000>;
621 #address-cells = <0>;
632 bus-range = <0x20 0x2f>;
647 interrupt-map-mask = <0 0 0 7>;
648 interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
649 <0 0 0 2 &pcie2x1l0_intc 1>,
650 <0 0 0 3 &pcie2x1l0_intc 2>,
651 <0 0 0 4 &pcie2x1l0_intc 3>;
657 msi-map = <0x2000 &its0 0x2000 0x1000>;
661 ranges = <0x00000800 0x0 0xf2000000 0x0 0xf2000000 0x0 0x100000
662 0x81000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x100000
663 0x82000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0xe00000
664 0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
665 reg = <0x0 0xfe170000 0x0 0x10000>,
666 <0xa 0x40800000 0x0 0x400000>;
675 #address-cells = <0>;
684 reg = <0x0 0xfe1b0000 0x0 0x10000>;
691 reg = <0x0 0xfe1b0000 0x0 0x10000>;
717 #address-cells = <0x1>;
718 #size-cells = <0x0>;
724 snps,blen = <0 0 0 0 16 8 4>;
740 reg = <0 0xfe220000 0 0x1000>;
749 ports-implemented = <0x1>;
755 reg = <0x0 0xfed70000 0x0 0x2000>;
762 #phy-cells = <0>;
768 reg = <0x0 0xfed70000 0x0 0x2000>;
778 #phy-cells = <0>;
782 #clock-cells = <0>;
790 reg = <0x0 0xfed90000 0x0 0x10000>;
809 #phy-cells = <0>;
814 #phy-cells = <0>;
821 reg = <0x0 0xfee10000 0x0 0x100>;
832 rockchip,pcie1ln-sel-bits = <0x100 0 0 0>;
838 reg = <0x0 0xfee80000 0x0 0x20000>;
839 #phy-cells = <0>;