Lines Matching full:cru
6 #include <dt-bindings/clock/rk3528-cru.h>
85 clocks = <&cru MCLK_SAI_I2S0>;
95 clocks = <&cru MCLK_SAI_I2S1>;
574 clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>,
575 <&cru HCLK_PCIE_DBI>, <&cru PCLK_CRU_PCIE>,
576 <&cru CLK_PCIE_AUX>, <&cru PCLK_PCIE>,
577 <&cru PCLK_PCIE_PHY>;
611 resets = <&cru SRST_RESETN_PCIE_POWER_UP>, <&cru SRST_PRESETN_PCIE>,
612 <&cru SRST_PRESETN_CRU_PCIE>;
627 clocks = <&cru CLK_REF_USB3OTG>, <&cru CLK_SUSPEND_USB3OTG>,
628 <&cru ACLK_USB3OTG>;
644 resets = <&cru SRST_ARESETN_USB3OTG>;
674 clocks = <&cru HCLK_USBHOST>,
675 <&cru HCLK_USBHOST_ARB>,
687 clocks = <&cru HCLK_USBHOST>,
688 <&cru HCLK_USBHOST_ARB>,
882 compatible = "rockchip,rk3528-grf-cru";
901 cru: clock-controller@ff4a0000 { label
902 compatible = "rockchip,rk3528-cru";
909 <&cru XIN_OSC0_DIV>,
910 <&cru PLL_GPLL>,
911 <&cru PLL_PPLL>,
912 <&cru PLL_CPLL>,
913 <&cru CLK_MATRIX_250M_SRC>,
914 <&cru CLK_MATRIX_500M_SRC>,
915 <&cru CLK_MATRIX_50M_SRC>,
916 <&cru CLK_MATRIX_100M_SRC>,
917 <&cru CLK_MATRIX_150M_SRC>,
918 <&cru CLK_MATRIX_200M_SRC>,
919 <&cru CLK_MATRIX_300M_SRC>,
920 <&cru CLK_MATRIX_339M_SRC>,
921 <&cru CLK_MATRIX_400M_SRC>,
922 <&cru CLK_MATRIX_600M_SRC>,
923 <&cru CLK_PPLL_50M_MATRIX>,
924 <&cru CLK_PPLL_100M_MATRIX>,
925 <&cru CLK_PPLL_125M_MATRIX>,
926 <&cru ACLK_BUS_VOPGL_ROOT>,
927 <&cru ACLK_VO_ROOT>,
928 <&cru ACLK_VPU_ROOT>,
929 <&cru ACLK_VPU_L_ROOT>;
974 clocks = <&cru ACLK_GPU_MALI>,
975 <&cru PCLK_GPU_ROOT>;
1000 clocks = <&cru PCLK_PMU_MAILBOX>;
1024 clocks = <&scmi_clk SCMI_CLK_GPU>, <&cru ACLK_GPU_MALI>,
1025 <&cru PCLK_GPU_ROOT>;
1163 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>;
1166 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>;
1168 resets = <&cru SRST_ARESETN_RKVDEC>, <&cru SRST_HRESETN_RKVDEC>,
1169 <&cru SRST_RESETN_HEVC_CA_RKVDEC>;
1188 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>;
1200 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>, <&cru CLK_CORE_RKVENC>;
1203 resets = <&cru SRST_ARESETN_RKVENC>, <&cru SRST_HRESETN_RKVENC>,
1204 <&cru SRST_RESETN_CORE_RKVENC>;
1206 assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_CORE_RKVENC>;
1223 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>;
1235 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1238 assigned-clocks = <&cru ACLK_VPU>;
1240 resets = <&cru SRST_ARESETN_VPU>, <&cru SRST_HRESETN_VPU>;
1259 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1270 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1273 assigned-clocks = <&cru ACLK_VPU>;
1275 resets = <&cru SRST_ARESETN_VPU>, <&cru SRST_HRESETN_VPU>;
1294 clocks = <&cru ACLK_VOP>,
1295 <&cru HCLK_VOP>,
1296 <&cru DCLK_VOP0>,
1297 <&cru DCLK_VOP1>;
1302 assigned-clocks = <&cru DCLK_VOP0>;
1341 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1354 clocks = <&cru ACLK_RGA2E>, <&cru HCLK_RGA2E>, <&cru CLK_CORE_RGA2E>;
1368 clocks = <&cru ACLK_RGA2E>, <&cru HCLK_RGA2E>;
1378 clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>;
1381 assigned-clocks = <&cru ACLK_VDPP>, <&cru CLK_CORE_VDPP>;
1383 resets = <&cru SRST_ARESETN_VDPP>, <&cru SRST_HRESETN_VDPP>,
1384 <&cru SRST_RESETN_CORE_VDPP>;
1398 clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>;
1410 clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>;
1413 assigned-clocks = <&cru ACLK_VDPP>, <&cru CLK_CORE_VDPP>;
1415 resets = <&cru SRST_ARESETN_VDPP>, <&cru SRST_HRESETN_VDPP>,
1416 <&cru SRST_RESETN_CORE_VDPP>;
1433 clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>;
1436 assigned-clocks = <&cru ACLK_JPEG_DECODER>;
1439 resets = <&cru SRST_ARESETN_JPEG_DECODER>, <&cru SRST_HRESETN_JPEG_DECODER>;
1454 clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>;
1465 clocks = <&cru HCLK_CVBS>,
1466 <&cru PCLK_VCDCPHY>,
1467 <&cru DCLK_CVBS>,
1468 <&cru DCLK_4X_CVBS>;
1509 clocks = <&cru ACLK_HDCP>, <&cru PCLK_HDCP>,
1510 <&cru HCLK_HDCP>;
1522 clocks = <&cru PCLK_HDMI>,
1523 <&cru CLK_SFR_HDMI>,
1524 <&cru CLK_CEC_HDMI>,
1571 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>, <&cru SCLK_IN_SPI0>;
1586 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>, <&cru SCLK_IN_SPI1>;
1599 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
1611 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1623 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1635 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1647 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1659 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1671 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1683 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1694 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
1707 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1720 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1733 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1746 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1759 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1772 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
1785 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
1801 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
1812 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
1823 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
1836 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
1847 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1858 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1869 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1882 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1891 clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
1898 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
1909 clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>, <&cru PCLK_TSADC>;
1911 assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>;
1913 resets = <&cru SRST_RESETN_TSADC>, <&cru SRST_PRESETN_TSADC>;
1917 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
1927 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
1929 resets = <&cru SRST_PRESETN_SARADC>;
1938 clocks = <&cru MCLK_SAI_I2S3>, <&cru HCLK_SAI_I2S3>;
1942 resets = <&cru SRST_MRESETN_SAI_I2S3>, <&cru SRST_HRESETN_SAI_I2S3>;
1952 clocks = <&cru MCLK_SAI_I2S0>, <&cru HCLK_SAI_I2S0>;
1956 resets = <&cru SRST_MRESETN_SAI_I2S0>, <&cru SRST_HRESETN_SAI_I2S0>;
1971 clocks = <&cru MCLK_SAI_I2S2>, <&cru HCLK_SAI_I2S2>;
1975 resets = <&cru SRST_MRESETN_SAI_I2S2>, <&cru SRST_HRESETN_SAI_I2S2>;
1985 clocks = <&cru MCLK_SAI_I2S1>, <&cru HCLK_SAI_I2S1>;
1989 resets = <&cru SRST_MRESETN_SAI_I2S1>, <&cru SRST_HRESETN_SAI_I2S1>;
2009 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
2031 clocks = <&cru MCLK_SPDIF>, <&cru HCLK_SPDIF>;
2045 clocks = <&cru CLK_GMAC0_SRC>, <&cru CLK_GMAC0_RMII_50M>,
2046 <&cru CLK_GMAC0_RX>, <&cru CLK_GMAC0_TX>,
2047 <&cru PCLK_MAC_VO>, <&cru ACLK_MAC_VO>;
2051 resets = <&cru SRST_ARESETN_MAC_VO>;
2076 clocks = <&cru CLK_MACPHY>;
2077 resets = <&cru SRST_RESETN_MACPHY>;
2110 clocks = <&cru CLK_GMAC1_SRC_VPU>, <&cru CLK_GMAC1_RMII_VPU>,
2111 <&cru PCLK_MAC_VPU>, <&cru ACLK_MAC_VPU>;
2114 resets = <&cru SRST_ARESETN_MAC>;
2153 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>;
2155 clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>,
2156 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
2157 <&cru TCLK_EMMC>;
2159 resets = <&cru SRST_CRESETN_EMMC>, <&cru SRST_HRESETN_EMMC>,
2160 <&cru SRST_ARESETN_EMMC>, <&cru SRST_BRESETN_EMMC>,
2161 <&cru SRST_TRESETN_EMMC>;
2171 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
2173 assigned-clocks = <&cru SCLK_SFC>;
2186 clocks = <&cru HCLK_SDIO0>, <&cru CCLK_SRC_SDIO0>,
2190 resets = <&cru SRST_HRESETN_SDIO0>;
2202 clocks = <&cru HCLK_SDIO1>, <&cru CCLK_SRC_SDIO1>,
2206 resets = <&cru SRST_HRESETN_SDIO1>;
2218 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>,
2222 resets = <&cru SRST_HRESETN_SDMMC0>;
2237 resets = <&cru SRST_RESETN_CORE_CRYPTO>;
2248 resets = <&cru SRST_HRESETN_TRNG_NS>;
2258 clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>,
2259 <&cru PCLK_OTPC_NS>;
2261 resets = <&cru SRST_RESETN_USER_OTPC_NS>,
2262 <&cru SRST_RESETN_SBPI_OTPC_NS>,
2263 <&cru SRST_PRESETN_OTPC_NS>;
2333 clocks = <&cru ACLK_DMAC>;
2350 clocks = <&cru CLK_REF_PCIE_INNER_PHY>, <&cru PCLK_PCIE_PHY>, <&cru PCLK_PIPE_GRF>;
2352 assigned-clocks = <&cru CLK_REF_PCIE_INNER_PHY>;
2354 resets = <&cru SRST_PRESETN_PCIE_PHY>, <&cru SRST_RESETN_PCIE_PIPE_PHY>;
2364 clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>;
2394 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>;
2409 clocks = <&cru PCLK_ACODEC>, <&cru MCLK_ACODEC_TX>;
2411 resets = <&cru SRST_PRESETN_ACODEC>;
2427 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
2439 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
2451 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
2463 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
2475 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;