Lines Matching +full:0 +full:xffb80000
63 #clock-cells = <0>;
70 #clock-cells = <0>;
71 clock-frequency = <0>;
77 #clock-cells = <0>;
78 clock-frequency = <0>;
84 reg = <0 0xff340014 0 0x4>;
86 #clock-cells = <0>;
94 reg = <0 0xff320004 0 0x4>;
96 #clock-cells = <0>;
105 #size-cells = <0>;
124 cpu0: cpu@0 {
127 reg = <0x0 0x0>;
139 reg = <0x0 0x1>;
149 reg = <0x0 0x2>;
159 reg = <0x0 0x3>;
172 arm,psci-suspend-param = <0x0010000>;
182 arm,psci-suspend-param = <0x0010000>;
201 0 1320 0
215 rockchip,pvtm-offset = <0x18>;
220 rockchip,pvtm-temp-prop = <0 0>;
382 auto-freq-en = <0>;
398 1 10 0
434 arm,smc-id = <0x82000010>;
436 #size-cells = <0>;
439 reg = <0x14>;
468 rockchip,sleep-debug-en = <0>;
470 (0
475 (0
504 thermal-sensors = <&tsadc 0>;
507 threshold: trip-point-0 {
552 reg = <0x0 0x0010f000 0x0 0x100>;
557 reg = <0x0 0xfe480000 0x0 0xc000>;
561 ranges = <0x0 0x0 0xfe480000 0xc000>;
564 rkvdec_sram: rkvdec-sram@0 {
565 reg = <0x0 0xc000>;
573 bus-range = <0x0 0xff>;
591 interrupt-map-mask = <0 0 0 7>;
592 interrupt-map = <0 0 0 1 &pcie2x1_intc 0>,
593 <0 0 0 2 &pcie2x1_intc 1>,
594 <0 0 0 3 &pcie2x1_intc 2>,
595 <0 0 0 4 &pcie2x1_intc 3>;
596 linux,pci-domain = <0>;
604 ranges = <0x00000800 0x0 0xfc000000 0x0 0xfc000000 0x0 0x100000
605 0x81000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000
606 0x82000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000
607 0xc3000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>;
608 reg = <0x0 0xfe4f0000 0x0 0x10000>,
609 <0x1 0x40000000 0x0 0x400000>;
618 #address-cells = <0>;
638 reg = <0x0 0xfe500000 0x0 0x400000>;
661 #address-cells = <0>;
663 reg = <0x0 0xfed01000 0 0x1000>,
664 <0x0 0xfed02000 0 0x2000>,
665 <0x0 0xfed04000 0 0x2000>,
666 <0x0 0xfed06000 0 0x2000>;
672 reg = <0x0 0xff100000 0x0 0x40000>;
685 reg = <0x0 0xff140000 0x0 0x40000>;
698 reg = <0x0 0xff190000 0x0 0x1000>,
699 <0x0 0xff192000 0x0 0x1000>,
700 <0x0 0xff194000 0x0 0x1000>,
701 <0x0 0xff196000 0x0 0x1000>;
706 reg = <0x0 0xff200000 0x0 0x20>;
711 reg = <0x0 0xff200080 0x0 0x20>;
716 reg = <0x0 0xff200100 0x0 0x20>;
721 reg = <0x0 0xff200200 0x0 0x20>;
726 reg = <0x0 0xff200280 0x0 0x20>;
731 reg = <0x0 0xff200300 0x0 0x20>;
736 reg = <0x0 0xff200380 0x0 0x20>;
741 reg = <0x0 0xff210000 0x0 0x20>;
746 reg = <0x0 0xff210080 0x0 0x20>;
751 reg = <0x0 0xff220000 0x0 0x20>;
756 reg = <0x0 0xff220080 0x0 0x20>;
761 reg = <0x0 0xff240000 0x0 0x20>;
766 reg = <0x0 0xff250000 0x0 0x20>;
771 reg = <0x0 0xff260000 0x0 0x20>;
776 reg = <0x0 0xff270000 0x0 0x20>;
781 reg = <0x0 0xff270080 0x0 0x20>;
786 reg = <0x0 0xff270100 0x0 0x20>;
791 reg = <0x0 0xff270200 0x0 0x20>;
796 reg = <0x0 0xff270280 0x0 0x20>;
801 reg = <0x0 0xff270300 0x0 0x20>;
806 reg = <0x0 0xff270380 0x0 0x20>;
811 reg = <0x0 0xff270480 0x0 0x20>;
816 reg = <0x0 0xff270500 0x0 0x20>;
821 reg = <0x0 0xff280000 0x0 0x20>;
826 reg = <0x0 0xff280080 0x0 0x20>;
831 reg = <0x0 0xff280100 0x0 0x20>;
836 reg = <0x0 0xff280180 0x0 0x20>;
841 reg = <0x0 0xff280200 0x0 0x20>;
846 reg = <0x0 0xff280280 0x0 0x20>;
851 reg = <0x0 0xff280300 0x0 0x20>;
856 reg = <0x0 0xff280380 0x0 0x20>;
861 reg = <0x0 0xff280400 0x0 0x20>;
866 * CORE_GRF: 0xff300000
867 * GPU_GRF: 0xff310000
868 * RKVENC_GRF: 0xff320000
869 * DDR_GRF: 0xff330000
870 * VPU_GRF: 0xff340000
871 * COMBO_PIPE_PHY_GRF: 0xff348000
872 * RKVDEC_GRF: 0xff350000
873 * VO_GRF: 0xff360000
874 * PMU_GRF: 0xff370000
875 * SYS_GRF: 0xff380000
879 reg = <0x0 0xff300000 0x0 0x90000>;
888 offset = <0x70200>;
903 reg = <0x0 0xff4a0000 0x0 0x30000>;
957 reg = <0x0 0xff540000 0x0 0x40000>;
962 reg = <0x0 0xff600000 0x0 0x2000>;
968 #size-cells = <0>;
998 reg = <0x0 0xff630000 0x0 0x200>;
1008 reg = <0x0 0xff700000 0x0 0x40000>;
1038 ls = <(-15658) 67354 0>;
1054 0 750 0
1065 rockchip,pvtm-offset = <0x10018>;
1070 rockchip,pvtm-temp-prop = <0 0>;
1142 1 22 0
1159 reg = <0x0 0xff740100 0x0 0x400>, <0x0 0xff740000 0x0 0x100>;
1165 rockchip,normal-rates = <340000000>, <0>, <600000000>;
1173 rockchip,taskqueue-node = <0>;
1174 rockchip,resetgroup-node = <0>;
1178 rockchip,rcb-iova = <0x10000000 65536>;
1185 reg = <0x0 0xff740800 0x0 0x40>, <0x0 0xff740900 0x0 0x40>;
1190 #iommu-cells = <0>;
1197 reg = <0x0 0xff780000 0x0 0x6000>;
1202 rockchip,normal-rates = <300000000>, <0>, <300000000>;
1211 rockchip,grf-mem-offset = <0x20010>;
1212 rockchip,grf-mem-values = <0x00000021>, <0xffff0021>;
1220 reg = <0x0 0xff78f000 0x0 0x40>;
1225 #iommu-cells = <0>;
1232 reg = <0x0 0xff7c0400 0x0 0x400>;
1237 rockchip,normal-rates = <300000000>, <0>;
1245 rockchip,grf-mem-offset = <0x40034>;
1246 rockchip,grf-mem-values = <0x0f040000>, <0x0f040f04>;
1255 reg = <0x0 0xff7c0800 0x0 0x40>;
1260 #iommu-cells = <0>;
1267 reg = <0x0 0xff7c1000 0x0 0x200>;
1272 rockchip,normal-rates = <300000000>, <0>;
1287 reg = <0x0 0xff840000 0x0 0x3000>,
1288 <0x0 0xff845000 0x0 0x1000>,
1289 <0x0 0xff846400 0x0 0x800>;
1310 #size-cells = <0>;
1312 port@0 {
1314 #size-cells = <0>;
1315 reg = <0>;
1317 vp0_out_hdmi: endpoint@0 {
1318 reg = <0>;
1325 #size-cells = <0>;
1328 vp1_out_tve: endpoint@0 {
1329 reg = <0>;
1338 reg = <0x0 0xff847e00 0x0 0x100>;
1343 #iommu-cells = <0>;
1351 reg = <0x0 0xff850000 0x0 0x1000>;
1358 rockchip,grf-offset = <0x600e0>;
1359 rockchip,grf-values = <0x0ff10000>, <0x0ff10ff1>;
1365 reg = <0x0 0xff850f00 0x0 0x100>;
1370 #iommu-cells = <0>;
1376 reg = <0x0 0xff860000 0x0 0x500>;
1380 rockchip,normal-rates = <340000000>, <0>, <340000000>;
1395 reg = <0x0 0xff860800 0x0 0x100>;
1400 #iommu-cells = <0>;
1407 reg = <0x0 0xff861000 0x0 0x100>, <0x0 0xff862000 0x0 0x900>;
1412 rockchip,normal-rates = <340000000>, <0>, <340000000>;
1420 rockchip,grf-mem-offset = <0x600e0>;
1421 rockchip,grf-mem-values = <0xf0040000>, <0xf004f004>;
1431 reg = <0x0 0xff870000 0x0 0x400>;
1435 rockchip,normal-rates = <340000000>, <0>;
1450 reg = <0x0 0xff870480 0x0 0x40>;
1455 #iommu-cells = <0>;
1462 reg = <0x0 0xff880000 0x0 0x4000>,
1463 <0x0 0xffde0000 0x0 0x300>;
1473 rockchip,lumafilter0 = <0x0ff80006>;
1474 rockchip,lumafilter1 = <0x00090010>;
1475 rockchip,lumafilter2 = <0x0ffb0fd8>;
1476 rockchip,lumafilter3 = <0x00080057>;
1477 rockchip,lumafilter4 = <0x0fef0f64>;
1478 rockchip,lumafilter5 = <0x0016010a>;
1479 rockchip,lumafilter6 = <0x0f830df7>;
1480 rockchip,lumafilter7 = <0x08de055f>;
1489 #size-cells = <0>;
1491 port@0 {
1492 reg = <0>;
1494 #size-cells = <0>;
1496 tve_in_vp1: endpoint@0 {
1497 reg = <0>;
1507 reg = <0x0 0xff8c0000 0x0 0x2000>;
1517 reg = <0x0 0xff8d0000 0x0 0x20000>,
1518 <0x0 0xff610000 0x0 0x200>;
1532 pinctrl-0 = <&hdmi_pins>;
1536 #sound-dai-cells = <0>;
1542 #size-cells = <0>;
1544 port@0 {
1545 reg = <0>;
1547 #size-cells = <0>;
1549 hdmi_in_vp0: endpoint@0 {
1550 reg = <0>;
1559 reg = <0x0 0xff930000 0x0 0x400>;
1567 reg = <0x0 0xff9c0000 0x0 0x1000>;
1570 #size-cells = <0>;
1576 pinctrl-0 = <&spi0_csn0 &spi0_csn1 &spi0_pins>;
1582 reg = <0x0 0xff9d0000 0x0 0x1000>;
1585 #size-cells = <0>;
1591 pinctrl-0 = <&spi1_csn0 &spi1_csn1 &spi1_pins>;
1597 reg = <0x0 0xff9f0000 0x0 0x100>;
1609 reg = <0x0 0xff9f8000 0x0 0x100>;
1621 reg = <0x0 0xffa00000 0x0 0x100>;
1633 reg = <0x0 0xffa08000 0x0 0x100>;
1645 reg = <0x0 0xffa10000 0x0 0x100>;
1657 reg = <0x0 0xffa18000 0x0 0x100>;
1669 reg = <0x0 0xffa20000 0x0 0x100>;
1681 reg = <0x0 0xffa28000 0x0 0x100>;
1693 reg = <0x0 0xffa50000 0x0 0x1000>;
1698 pinctrl-0 = <&i2c0m0_xfer>;
1700 #size-cells = <0>;
1706 reg = <0x0 0xffa58000 0x0 0x1000>;
1711 pinctrl-0 = <&i2c1m0_xfer>;
1713 #size-cells = <0>;
1719 reg = <0x0 0xffa60000 0x0 0x1000>;
1724 pinctrl-0 = <&i2c2m0_xfer>;
1726 #size-cells = <0>;
1732 reg = <0x0 0xffa68000 0x0 0x1000>;
1737 pinctrl-0 = <&i2c3m0_xfer>;
1739 #size-cells = <0>;
1745 reg = <0x0 0xffa70000 0x0 0x1000>;
1750 pinctrl-0 = <&i2c4_xfer>;
1752 #size-cells = <0>;
1758 reg = <0x0 0xffa78000 0x0 0x1000>;
1763 pinctrl-0 = <&i2c5m0_xfer>;
1765 #size-cells = <0>;
1771 reg = <0x0 0xffa80000 0x0 0x1000>;
1776 pinctrl-0 = <&i2c6m0_xfer>;
1778 #size-cells = <0>;
1784 reg = <0x0 0xffa88000 0x0 0x1000>;
1789 pinctrl-0 = <&i2c7_xfer>;
1791 #size-cells = <0>;
1797 reg = <0x0 0xffa90000 0x0 0x10>;
1800 pinctrl-0 = <&pwm0m0_pins>;
1808 reg = <0x0 0xffa90010 0x0 0x10>;
1811 pinctrl-0 = <&pwm1m0_pins>;
1819 reg = <0x0 0xffa90020 0x0 0x10>;
1822 pinctrl-0 = <&pwm2m0_pins>;
1830 reg = <0x0 0xffa90030 0x0 0x10>;
1835 pinctrl-0 = <&pwm3m0_pins>;
1843 reg = <0x0 0xffa98000 0x0 0x10>;
1846 pinctrl-0 = <&pwm4m0_pins>;
1854 reg = <0x0 0xffa98010 0x0 0x10>;
1857 pinctrl-0 = <&pwm5m0_pins>;
1865 reg = <0x0 0xffa98020 0x0 0x10>;
1868 pinctrl-0 = <&pwm6m0_pins>;
1876 reg = <0x0 0xffa98030 0x0 0x10>;
1881 pinctrl-0 = <&pwm7m0_pins>;
1889 reg = <0x0 0xffab0000 0x0 0x20>;
1897 reg = <0x0 0xffac0000 0x0 0x100>;
1906 reg = <0x0 0xffad0000 0x0 0x400>;
1917 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
1918 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
1924 reg = <0x0 0xffae0000 0x0 0x10000>;
1936 reg = <0x0 0xffb70000 0x0 0x1000>;
1944 #sound-dai-cells = <0>;
1950 reg = <0x0 0xffb80000 0x0 0x1000>;
1954 dmas = <&dmac 1>, <&dmac 0>;
1959 pinctrl-0 = <&i2s0m0_lrck
1963 #sound-dai-cells = <0>;
1969 reg = <0x0 0xffb90000 0x0 0x1000>;
1977 #sound-dai-cells = <0>;
1983 reg = <0x0 0xffba0000 0x0 0x1000>;
1992 pinctrl-0 = <&i2s1_sclk
2002 #sound-dai-cells = <0>;
2008 reg = <0x0 0xffbb0000 0x0 0x1000>;
2014 pinctrl-0 = <&pdm_clk0
2020 #sound-dai-cells = <0>;
2026 reg = <0x0 0xffbc0000 0x0 0x1000>;
2032 #sound-dai-cells = <0>;
2034 pinctrl-0 = <&spdifm0_pins>;
2040 reg = <0x0 0xffbd0000 0x0 0x10000>;
2071 #address-cells = <0x1>;
2072 #size-cells = <0x0>;
2080 pinctrl-0 = <&fephym0_led_link &fephym0_led_spd>;
2089 snps,blen = <0 0 0 0 16 8 4>;
2105 reg = <0x0 0xffbe0000 0x0 0x10000>;
2128 #address-cells = <0x1>;
2129 #size-cells = <0x0>;
2135 snps,blen = <0 0 0 0 16 8 4>;
2151 reg = <0x0 0xffbf0000 0x0 0x10000>;
2169 reg = <0x0 0xffc00000 0x0 0x4000>;
2176 #size-cells = <0>;
2183 reg = <0x0 0xffc10000 0x0 0x4000>;
2189 fifo-depth = <0x100>;
2199 reg = <0x0 0xffc20000 0x0 0x4000>;
2205 fifo-depth = <0x100>;
2215 reg = <0x0 0xffc30000 0x0 0x4000>;
2221 fifo-depth = <0x100>;
2230 reg = <0x0 0xffc40000 0x0 0x2000>;
2244 reg = <0x0 0xffc50000 0x0 0x200>;
2255 reg = <0x0 0xffce0000 0x0 0x4000>;
2268 reg = <0x02 0x2>;
2271 reg = <0x08 0x1>;
2275 reg = <0x09 0x1>;
2276 bits = <0 3>;
2279 reg = <0x09 0x1>;
2283 reg = <0x09 0x1>;
2287 reg = <0x0a 0x10>;
2290 reg = <0x1a 0x1>;
2293 reg = <0x1b 0x1>;
2296 reg = <0x1c 0x1>;
2299 reg = <0x29 0x1>;
2302 reg = <0x2d 0x1>;
2305 reg = <0x2e 0x2>;
2308 reg = <0x30 0x1>;
2311 reg = <0x32 0x6>;
2314 reg = <0x38 0x6>;
2317 reg = <0x3e 0x6>;
2323 reg = <0x0 0xffd60000 0x0 0x4000>;
2324 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
2341 reg = <0x0 0xffd70000 0x0 0x100>;
2348 reg = <0x0 0xffdc0000 0x0 0x10000>;
2363 reg = <0x0 0xffdf0000 0x0 0x10000>;
2366 #clock-cells = <0>;
2371 #phy-cells = <0>;
2382 #phy-cells = <0>;
2391 reg = <0x0 0xffe00000 0x0 0x10000>;
2393 #phy-cells = <0>;
2399 #clock-cells = <0>;
2407 reg = <0x0 0xffe10000 0x0 0x1000>;
2408 #sound-dai-cells = <0>;
2425 reg = <0x0 0xff610000 0x0 0x200>;
2430 gpio-ranges = <&pinctrl 0 0 32>;
2437 reg = <0x0 0xffaf0000 0x0 0x200>;
2442 gpio-ranges = <&pinctrl 0 32 32>;
2449 reg = <0x0 0xffb00000 0x0 0x200>;
2454 gpio-ranges = <&pinctrl 0 64 32>;
2461 reg = <0x0 0xffb10000 0x0 0x200>;
2466 gpio-ranges = <&pinctrl 0 96 32>;
2473 reg = <0x0 0xffb20000 0x0 0x200>;
2478 gpio-ranges = <&pinctrl 0 128 32>;